Clock GatingIn CMOS, Power Management-4

In this article, we delve into the intricate topic of clock gating in CMOS circuits, providing a comprehensive overview. We start by discussing the importance of power management and how clock gating plays a crucial role in reducing power consumption. The article compares clock-gated registers with non-clock-gated registers, highlighting the differences in performance and efficiency. We then explore various types of clock gating techniques, including AND-based, latch-based, flip flop-based, and MUX-based methods, along with bus-specific clock gating (BSCG) and its optimized version (OBCG). Further, we cover local explicit clock gating (LECG), enhanced clock gating (ECG), and typical clock gating circuits, emphasizing type and delay matching, multiple-stage implementations, and the overall advantages and challenges associated with clock gating.

Power Management & Clock Gating:

Clock gating, very effective in reducing the power consumption. This technique reduces power consumption by using a clock gater. Clock gater /turn off the clock that is driving a part of the logic when it's not required.  It will not affect the original functionality of the design.  The goal of this technique is to disable/suppress propagation of transitions to some parts of the clock path under certain condition.

Power savings happen due to :

(1) reduction in switching capacitance in the clock network

(2) reduction in switching activity in the logic fed by the storage elements since unnecessary transitions are not loaded when the clock is not active.

The clock signal is computed by function fcg. CLK is the system clock and CLKG the gated clock of the functional unit.

Automatic clock gating is supported by modern EDA tools. They identify the circuits where clock gating can be inserted.

There are many clock gating styles implemented to optimize power in VLSI circuits :  

(1) Latch-free based design,

(2) Latch-based design

Clock Gated vs. Non-Clock Gated Registers :

1. Non Clock gated Register :

2. Clock gated Register :

3. Non Clock Gating Ckt without Enable :

4. Non Clock Gating Ckt with Enable :

Different Types of Clock Gating :

Commonly used clock gating techniques:

1. AND Based Clock Gating

2. Latch Based Clock Gating

3. Flip Flop Based Clock Gating

4. MUX Based Clock Gating

Advanced clock gating schemes :

(A) Clock Gating Without Enable Signal :

1. Bus Specific Clock Gating (BSC)

2. Threshold based clock gating (TCG)

3. Optimized bus specific clock gating (OBSC)

(B) Clock Gating With Enable Signal

1. Local explicit clock gating (LECG)

2. Enhanced clock gating (ECG)

AND Based Clock Gating :

In AND gate based scheme the enable signal explicitly control the clock input to the logic block. Here if enable signal goes inactive between the clock pulse, clock output prematurely terminates(hazard problem). Or if En goes multiple times on and off between clock pulses then it generates multiple clock pulses. This restriction makes this circuit inappropriate.

Latch Based Clock Gating :

The latch based clock gating style adds a level- sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. The anomaly occurs when enable signal changes during the sleep period leading to an incorrect design. Here hazard problem that exits in AND gate design is removed but glitch problems is still there.

Flip Flop Based Clock Gating :

A similar technique to latch based design with one difference that instead of latch, D flip flop is used here. The same anomaly which existed in latch based design exists here too with longer sleep period. So the probability of missing the

change on the enable pin is high. Therefore this technique is not used much. Also area overhead increases much in comparison to latch based technique.

MUX Based Clock Gating :

In this technique the feedback path is controlled by the mux. Mux is controlled by select line when it is required to close or open the feedback path. This circuit is simple robust and often a reasonable choice. But this circuit uses one fairly expensive mux per bit and consume more power.

Bus Specific Clock Gating (BSCG) :

BSCG is used to reduce the dynamic power and it can be realized using D-flip-flops, AND, XOR and OR gates.

BSCG circuit compares the inputs and outputs and gates the clock when they are equal. When there is change in the input data of gated FFs then only the gated clock is applying for D-FFs otherwise the gated clock signal is not applying. Power consumption will be high if output toggle rate increases which indicates high switching activity of the signal.

Threshold Based Clock Gating (TCG) is another data driven clock gating technique. In this technique toggle rates of FFs of non-clock gating circuit need to be tested at first time, and then according to the list of toggle rate, those FFs are divided into two parts. In this way disadvantages of BSC technique is removed.

Optimized Bus-Specific Clock Gating (OBCG) :

This is a fine grained and activity-driven CG methodology.  The FFs are clustered based on relationship between them. The problem of gated FF selection is reduced from exponential complexity into linear. It works by comparing the inputs and outputs and gates the clock when they are equal.

Local Explicit Clock Gating (LECG) :

Here clock of Flip flop is gated explicitly by using enable signal. This enable signal increase the control of the circuit explicitly.  Here as long as EN=0 no clock is passed of flipflop and hence no power consumption, but power consumption starts when en is high i.e 1. If en=1 period is significantly high than over all power consumption increase due to additional circuitry which over weighs the savings.

Enhanced Clock Gating (ECG):

This method combines both BSCG and LECG and make use of the advantages of both methods. In BSCG switching activity increase the power dissipation which is eliminated by using EN signal which gated the circuit for that much period of time. If the mentioned situation is not emerged then this method consume more power because of complex circuit

than previous to methods.

Typical Clock Gating Circuit:

Clock gating can reduce the power consumed by flipflops and the clock distribution network.  A groups of flip-flops are identified and clock port of each FF connected with

the O/P of clock gating circuit.  A common enable signal is used to control the clock gating circuit .  Therefore, if a group of flipflops which share a common enable term have clock gating implemented, the flip- flopswill consume zero dynamic power as long as this enable term is false. 

There are two technique to implement

clock ­gating:

(1) Type matching

(2) Delay matching

Type Matching Clock Gating :

In type-matching clock gating same logic gates are used in same levels.

Delay Matching Clock Gating :

In delay matching clock gating cells with same timing requirements are used.

Multiple Stage Clock Gating:

Multi-stage clock gating style exists, where the clock gating is cascaded. The clock signal of the first stage clock gating (CG Stage 1) is gated by the second stage clock gating (CG Stage 2). The gated clock signal should arrive at CG Stage 1 earlier than the enable signals EN_A, EN_B and EN_C to maintain the functional correctness of the circuit. That is if EN_A, EN_B and EN_C depend on the outputs of other flip- flops in the circuit, the minimum delay of enablesignals EN_A, EN_B and EN_C should be larger than the gated clock.

Advantages & Challenges of Clock Gating :

(1) Dynamic power reduction :  In clock gating, clock signal does not reach idle parts of the circuit. Power is saved as switching activity minimized.

(2) Reduced Heat generation : Since switching is less, power

consumption reduces. As a result heat generation reduces.

(3) Enhanced Battery Life : For battery powered movable devices like smartphones and laptops, clock gating is very useful. Since power dissipation reduces , battery life increases.

Challenges of Clock Gating :

(1) Timing Violations : Introduction of gating logic may lead to setup and hold time violations.

(2) Synchronization Issue : Since the clock is enabled and disabled in various parts , that might lead to synchronization problem.

(3) Delay : Introduction of extra logic of clock gating may introduce clock path.

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Understanding Filler Cells in VLSI: A Comprehensive Guide

In this article, we delve into the world of VLSI and explore the concept of filler cells. We discuss the purpose and importance of these cells in the design process and their impact on the overall performance of the circuit. Whether you're a beginner or an experienced engineer, this comprehensive guide will provide valuable insights into the role of filler cells in VLSI.

Standard Cell Layout:

The Standard Cells are of equal heights (a.k.a Track) but width may vary. Standard Cells are placed in rows with cells butting against each other. This ensures continuous wells across the entire row.  This helps in fabrication and mask design of the design. Such arrangement allows one to run common power lines such as power(VDD) and ground(GND/VSS) 

through the cell array. This ensures VDD/GND rails (follow pins) are fully connected. A desired design is implemented by picking up necessary standard cell from different such rows/column and interconnecting them as per the target functionality.

Standard Cell Layout & Filler Cell:

This tiled structure of standard cells are optimized for area. However Standard cell placement never reaches 100% utilization. Any blank space in the tile structure is filled up with a special cell called Filler Cell or DeCap Cells from the Standard Cell Library. This ensure proper GDS layers to pass DRC and sufficient diffusion and poly densities. The Filler Cell is a empty cell with power and ground rails. Empty means that cell has no functionality. It has physical exsistance that is it has physical layers like diffusion layer etc. Total effective area is calculated by subtracting the sum of all filler cell area from total area of Standard Cells Tile Structure. Chip Finishing for SignOff includes, at the very least: Insertion of Fillers and DeCaps.

Design Automation for Placing Filler Cell :

Filler Cells are inserted after all cells have been placed and the confidence factor of a design in meeting timing is high. Filler cells will fill in all row spaces, which remain open. The PnR Tools in VLSI generally accepts TCL Scripting for automation. The TCL script traverses the standard cell row (from left to right), it checks the adjacent cell edges. If the edges match, the TCL script moves to the next cell. However, if the edges do not match, the script checks if the opposite side of the right cell matches the current cell edge. If it does, the script flips the cell and continues. If neither sides match, then a filler cell is placed in between the cells, to ensure that design rules are satisfied. As power rails (horizontal power lines) are usually built into the standard cells as feed- through. Leaving any space in the row would result in a break in the power line.

Physical Design Aspect :

A set of physical-only cells (without any boolean function) in the form of fillers and decap cells are provided in standard cell distribution as they are required during digital implementation. Fillers Cells are important as they connect the active implants (n+ and p+), as well as n-wells and power rails throughout an entire row. Fillers should come in various distinct widths, where the width is an integer multiple of the metal one routing pitch (track). Fillers consist of dummy polysilicon and diffusion area, which improves density. Some filler cells may include the well-taps which aid in lowering the substrate resistance. Both Tie-low and Tie-high filler cells are provided to avoid direct connections (ESD prevention) to power and ground rails when there is need for a constant input. Finally some decap cells are provided to help mitigate IR drop issues during digital implementation.

Physical Verification (DRC) Aspect:

Commercial P&R tools apparently fix the minimum implant area (MinIA) violations by inserting filler cells at the final design stage. For example, One commercial tool has a utility to define an implant layer group for filler cells, so that each narrow cell can be padded filler cells having the same implant type. Another commercial tool checks and fixes implant area violations according to the rules specified in LEF, during placement and filler cell insertion. Another commercial tool offers a Voltage-threshold-aware filler cell insertion flow according to which users can define the Vt filler cells to be inserted between different Vt regions. For example, users can insert NVT filler cells between NVT and HVT cells, and LVT filler cells between LVT and NVT cells.

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Power Gating in CMOS Technology: Power Management 3

In this article, we have comprehensively discussed power gating in CMOS circuits, providing a detailed overview of its principles and applications. We began by exploring power management strategies, focusing on how power gating can be effectively implemented in System on Chip (SoC) designs. Key topics included the retention strategy, various circuit configurations, and critical power gating parameters. We differentiated between global and local power gating, delving into specific techniques like switch-in cell gating and the distinctions between fine and coarse grain power gating. Additionally, we examined different implementation styles, such as ring and column style, and discussed the figures of merit that evaluate the effectiveness of power gating in circuit designs.

Power Management & Power Gating :

The basic idea of power management arise from the fact that all parts of a circuit are not needed to function all the time. The power management scheme can identify conditions under which either certain parts of the circuit or the entire circuit can remain idle and shut them down to reduce power consumption. One of the technique to reduce the leakage power. In this technique a MOSFET switch or sleep transistor is used to cut off/gate, a circuit from the power rails (Vdd and/or gnd) during standby mode. The switch typically is positioned as header between the circuit and the Vdd or as footer between the circuit and the ground. Power gating has 2 modes : Sleep/Stand By mode & Active mode. During active operation, the power gating switch remains on, supplying the current that the circuit uses to operate. During standby mode, turning off the power gating switch reduces the current dissipated through the circuit.

Power Gated SoC :

There are three major components of a power gated SoC.

Power Switches : A power switch is a PMOS/NMOS transistor that disconnects the circuit from the power supply, ground,  or both power and ground networks, when power gating is engaged. 

Isolation Cells : Isolation Cell is placed between power gated block and the active/always ON block. During Power Gating operation, the circuit will contain few ON and OFF domains together at any point of time. In such situation, output of a OFF domain sends invalid signal to the ON Domain. To deal with such problematic situation Isolation Cell is placed.

Controller : Controllers are used in standard power gating applications to control and synchronize local power switches and isolation cells with clock gating or power gating signals.

Retention Strategy :

A retention strategy is required otherwise all state information is lost when the block is powered down. To resume its operation on power up, the block must either have its state restored from an external source or build up its state from the reset condition. In either case, the time and power required can be significant. One of the following three approaches may be used:

(1) Software Approach : In the software approach, the always-ON CPU reads the registers of the power-gated blocks and stores in the processor’s memory. During power-up sequence, the CPU writes back the registers from the memory.

(2) Scan-based Approach : Scan-Based Approach Scan chains used for built-in self-test (BIST) can be reused. During power-down sequence, the scan register outputs are routed to an on-chip or off-chip memory. In this approach, there can be significant saving of chip area.

(3) Register-based Approach : Standard registers are replaced by retention registers, that contains a shadow register which can preserve the registers state during power down and restore it at power up.

Circuit Configuration :

(1) Sleep Technique : 

(2) Zig-zag Method :

(3) Sleepy Stack Method : 

(4) Dual-Sleep Method :

(5) Dual Stack Method :

Power Gating Parameters :

Power Gate Size : The power gate size is selected to handle the amount of switching current at any given time. The gate must be bigger such that there is no measurable voltage (IR) drop due to the gate. As a rule of thumb, the gate size is selected to be around 3 times the switching capacitance. Designers can also choose between header (P-MOS) or footer (N-MOS) gate. Usually footer gates tend to be smaller in area for the same switching current. Dynamic power analysis tools can accurately measure the switching current and also predict the size for the power gate.

Gate Control Slew Rate : In power gating, this is an important parameter that determines the power gating efficiency. When the slew rate is large, it takes more time to switch off and switch-on the circuit and hence can affect the power gating efficiency. Slew rate is controlled through buffering the gate control signal.

Simultaneous Switching Capacitance : This important constraint refers to the amount of circuit that can be switched simultaneously without affecting the power network integrity. If a large amount of the circuit is switched simultaneously, the resulting “rush current” can compromise the power network integrity. The circuit needs to be switched in stages in order to prevent this.

Power Gate Leakage : Since power gates are made of active transistors, leakage reduction is an important consideration to maximize power savings.

Power-Gating Topologies :

1. Global Power Gating :

Global power gating refers to a logical topology in which multiple switches are connected to one or more blocks of logic, and a single virtual ground is shared in common among all the power-gated logic blocks. This topology is effective for large blocks (coarse- grained) in which all the logic is power gated, but is less effective, for physical design reasons when the logic blocks are small. It does not apply when there are many different power-gated blocks, each controlled by a different sleep enable signal.

2. Local Power Gating :

Local power gating refers to a logical topology in which each switch singularly gates its own virtual ground connected to its own group of logic. This arrangement results in multiple segmented virtual grounds for a single sleep domain.

3. Switch in Cell Gating :

Switch in cell may be thought of as an extreme form of local power-gating implementation. In this topology, each logic cell contains its own switch transistor. Its primary advantages are that delay calculation is very straightforward. The area overhead is substantial in this approach.

Power-Gating Granularity :

1. Fine Grain Power Gating:

The power-gating switch is placed locally as part of the standard cell. As a result the size of the switch is usually large and there is significant area overhead. All cell had VGND port . All cells in a domain share same VGND port.

2. Coarse Grain Power Gating:

A relatively larger block or a block of gates is power switched by a block of switch cells. IP Core is surrounded by VGND. Switch is between VGND and GND

Power-Gating Implimentation :

1. Ring Style Implementation :

Switches are placed external to the power-gated block by encapsulating it by a ring of switches. Switches connect VDD to the virtual VVDD of the power-gated block. This is the only style that can be used to supply power to an existing hard block by placing the switches outside it.

2. Grid Style Implementation :

The switch cells are added as multiple columns within the logic block. Here the global power grid inside the block is routed in the higher metal layers, while the switched power rails are routed in lower layers.

Figures Of Merit For Power-Gating

Performance Degradation (α): A design/input specification that defines the maximum allowable delay increase in the design/logic block. Increase in the original critical path delay permitted when the design/logic block is power-gated. This parameter is denoted by α, expressed as the percentage increase in the original critical path delay.

Sleep Transistor Size (Wsleep): Sleep transistor size depends mainly on two parameters: (i) The virtual ground voltage, VVGN D ; (ii) The peak discharge current of the design/logic block, Ipeak . For a given peak current value Ipeak, one can have a lower VVGND value to obtain a lower speed degradation of the cells in the power- gated design, thus resulting in a larger sleep transistor. On the other hand, a higher value of VVGND would lead to a smaller sleep transistor, but to a higher delay degradation of the cells in the power-gated design.

Leakage Power Savings: The main benifit of power-gating is how much leakage power can be saved. 

Power Mode Transition Time (PMt): In a power-gated design/block, the turn-off time is the time required by the design/block to go from the active to the stand-by mode, and the turn-on time as the time required by the design/block to make the opposite mode transition.

Power-mode transition energy (PMe): This quantity denotes a non-negligible energy dissipation during turn-on/off of the sleep transistor. The energy loss occurs in the charging and discharging of the virtual ground line capacitance and in the buffers which drive the sleep transistor. This parameter is strongly coupled with the size of the sleep transistor.

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What is the definition of VLSI design? What is the average salary for this profession?

 

VLSI (Very Large Scale Integration) design is the process of designing integrated circuits (ICs) by combining thousands or millions of transistors onto a single chip. The design process involves various stages such as architecture design, logic design, circuit design, and physical design. VLSI design is a highly specialized field that requires advanced knowledge of electronics, computer engineering, and mathematics.

Here is the ecosystem of VLSI.

The average salary for a VLSI designer can vary widely depending on their experience, location, and the company they work for. According to Glassdoor, the average base salary for a VLSI design engineer in the United States is around $105,000 per year, with salaries ranging from $80,000 to $135,000 per year. However, senior VLSI design engineers with many years of experience and expertise can earn significantly more than this average. Additionally, salaries for VLSI designers in other countries may differ from those in the United States.

For Salary In India (General Idea) watch this video.

For Compny specific CTC watch this video. 

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What is easy to learn in VLSI : frontend or backend?

Both frontend and backend design in VLSI have their own challenges and complexities, and it ultimately depends on the individual's prior knowledge, skills, and interests to determine which area is easier for them to learn.

In general, frontend design in VLSI involves designing the digital logic of the system using Hardware Description Languages (HDLs) like Verilog or VHDL. This includes tasks such as designing and verifying logic circuits, simulation, and RTL coding. Frontend design requires a good understanding of digital circuits and programming skills.

On the other hand, backend design in VLSI involves physical design aspects such as floor planning, placement, routing, and timing analysis. Backend design requires knowledge of the fabrication process and an understanding of how the physical layout affects the performance of the design.

Both frontend and backend design are essential for developing VLSI systems. However, if you have experience in programming and digital circuits, frontend design may be easier for you to learn. If you have a background in physics and are interested in physical design, then backend design may be a better fit.

Here is a guide to choose between frontend and backend.

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What Is VLSI Design ?

VLSI design is a complex and highly specialized field that involves the creation of integrated circuits (ICs) that contain millions or even billions of electronic components on a single chip. These components can include transistors, diodes, resistors, capacitors, and other types of components that are commonly used in electronic circuits.

The VLSI design process consists of several stages, each of which requires a deep understanding of electronic theory, EDA computer-aided design (EDA-CAD) tools, and specialized manufacturing processes. The first stage is design specification, where engineers work with clients or project stakeholders to define the specific requirements and goals for the chip.

Once the design specifications are established, the circuit design stage begins. This involves using CAD tools to create a detailed layout of the circuit, including the placement and interconnections of each component. Logic verification follows, which is a critical step in ensuring that the circuit operates correctly and meets the design specifications.

Physical design is the next stage, where engineers create a layout that takes into account the physical constraints of the chip, including the size, power consumption, and thermal considerations. This is a highly technical and specialized process that requires extensive knowledge of manufacturing techniques, materials science, and physical modeling.

You can choose between 

FrontEnd(RTL Coding and Logic Verification) or BackEnd(Physical Design) based on your inclination : 

Try to understand various VLSI job role : here 

Finally, fabrication involves the actual production of the chip using specialized manufacturing processes such as lithography, deposition, etching, and polishing. These processes require sophisticated equipment and highly skilled technicians to ensure that the chip meets the design specifications and is free of defects.

You can enbroden your view of the VLSI Ecosystem :  here 

Overall, VLSI design is a critical technology that has enabled the creation of smaller, faster, and more powerful electronic devices. It has revolutionized the field of electronics and continues to be an important area of research and development for the semiconductor industry.

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