What does technology sovereignty really mean in a world where chips power everything? 💡 In this electrifying episode of The Semiconductor Podcast (TSP), we dive deep with John, founder of TechSovereign Partners, to explore the hidden truths, strategic blind spots, and untapped potential of the global semiconductor ecosystem 🌍🔍.
🎯 What’s in the episode?
🚀 John’s dynamic journey from industry insider to thought leader and founder
🧠 What vendor lock-in, tribal knowledge, and scientific identity drag really cost your fab
🏭 Why mature-node fabs might be your strongest weapon—and why the world keeps ignoring them
🌐 How countries like India can realistically build chip sovereignty
🧰 Practical frameworks for fabs to balance innovation and execution
🔁 The quiet crisis of talent loss and knowledge transfer in fabs—and how to fix it
🔓 A rethinking of IP, collaboration, and non-unique solutions in semiconductor ops
🏆 Real-world engagements where execution trumped theory—delivered by a globally seasoned team
🔥 Whether you're a fab engineer, policymaker, startup founder, or simply a semiconductor enthusiast, this episode is packed with insight bombs and actionable takeaways. You’ll leave with a new lens on how fabs work, why some fail, and what it takes to build resilient, sovereign, and scalable chip ecosystems.
👷♂️ Engineers, don’t miss this—this is the conversation behind the conversations.
📺 Watch now. Think deeper. Build smarter.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape.
Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : John Ghekiere
John Ghekiere is the principal and founder of TechSovereign Partners, a consulting firm that helps semiconductor manufacturers and equipment OEMs solve tough problems fast. Drawing on a network of deeply experienced technologists across key fab disciplines, the firm works with manufacturers worldwide to stabilize performance, resolve yield issues, and guide critical decisions around tool strategy and manufacturing readiness. Before founding TechSovereign, John held senior technical and executive roles at Semitool, Applied Materials, and ClassOne Technology.
Credits :
Image by Lucas Wendt from Pixabay
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Today, The Semiconductor Podcast (TSP) marks a milestone—25 guests from deep tech conversations, ecosystem insights, and stories that matter.
To every guest who joined us, shared their time, vision, and expertise—thank you. You've shaped this platform into a credible voice for the semiconductor and deep tech community.
To our listeners and viewers, your encouragement, feedback, and quiet support fuel our mission. Whether you’ve tuned in for one episode or twenty-five, you're part of this journey.
TSP was born from a simple idea: to spotlight innovators, technologists, and leaders shaping the future of semiconductors in India and beyond. We’re just getting started.
With gratitude and excitement, Let’s keep building the ecosystem—one conversation at a time.
In this episode of The Semiconductor Podcast (TSP), we dive deep into one of the most exciting frontiers in semiconductor innovation—memristors. Our distinguished guest Dr. Debashis Panda walks us through his professional journey, from early explorations in device fabrication and nanoscale characterization to cutting-edge research in neuromorphic computing and healthcare diagnostics.
We unpack:
🔋 What exactly are memristors, and why they’re poised to redefine non-volatile memory.
⚡ How memristors compare to traditional memory in power efficiency, scalability, and AI readiness.
🧠 The potential of memristors in overcoming the von Neumann bottleneck, powering edge AI, and mimicking brain-like synapses.
💉 Applications in healthcare, from real-time glucose monitoring to cancer diagnostics and treatment of neurological disorders.
👚 The role of transparent neuromorphic devices in wearables and next-gen medical tech.
🛠️ Insights into fabrication techniques, key materials like ZnO, and tools like AFM, and electron-beam lithography.
🌐 How interdisciplinary knowledge—spanning electronics, materials science, and biology—is driving innovation across computing, AI, and medical devices.
We also explore the evolving career landscape in semiconductors:
🇮🇳 Opportunities in India’s growing ecosystem post–India Semiconductor Mission.
📚 Skill sets in demand for roles in memory devices, neuromorphic systems, and quantum-edge convergence.
🚀 How young researchers and professionals can future-proof their careers in this fast-paced field.
Whether you’re a student, technologist, policymaker, or curious mind, this episode offers a window into the next decade of semiconductor-driven transformation.
🔗 Tune in to explore how memory, AI, and biology are converging to build the future of intelligent machines and healthcare. 🌟
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Dr. Debashis Panda
Dr. Debashis Panda received his Ph.D. from IIT Kharagpur, followed by post-doctoral research experiences at NCTU Taiwan, the University of Utah (USA), and the National University of Singapore (NUS). He is currently serving as a Professor at the University of Techno India Group.
Dr. Panda was awarded the prestigious Indian Academy of Sciences Summer Research Fellowship in 2016 and the INSA Visiting Scientist Fellowship in 2017. He has also served as a visiting scientist at NYCU Taiwan (2022), NCTU Taiwan (2019), NPL New Delhi (2016), and IIT Kharagpur (2017).
His current research interests include the design and fabrication of low-power, highly reliable, transparent, and flexible wearable artificial inorganic/organic synaptic memristors for neuromorphic computing. He is a Fellow of the Semiconductor Society of India, Indian Physical Society, and Materials Research Society of India.
Notably, Prof. Panda completed a DST-SERB project in December 2021. An ANRF-CRG project is currently ongoing since February 2024. Under his principal investigation, a DST iTBI project was also granted. Recently, a DAE-BRNS project has been approved with Dr. Panda as the Principal Investigator. Additionally, he received AICTE-STTP funding in August 2020 and coordinated an ATAL-funded FDP in January 2024.
Dr. Panda has published over 52 international peer-reviewed papers in SCI/Scopus-indexed journals, 70 international conference proceedings, one textbook, and three book chapters with reputed international publishers. His work has received more than 2,500 citations.
He is a reviewer for several prestigious journals, including those from Springer Nature, IEEE, AIP, RSC, IOP, ACS, and Elsevier. He also serves as an expert reviewer for SERB project grants, the International European Research Council, and Chile Government research project grants.
Dr. Panda maintains active research collaborations with NYCU Taiwan, NTHU Taiwan, Dongguk University (South Korea), the University of Porto (Portugal), and several IITs and NITs across India.
Watch the podcast here :
In this power-packed episode of The Semiconductor Podcast, we sit down with the visionary Managing Director of HCP Technologies to explore the extraordinary journey from an idea to a global player in semiconductor capital equipment. 💡🌍
We dive into:
🛠️ The origin story of HCP and its mission to innovate in India and beyond
📈 Strategic growth across EVs, mobile, cleanrooms, and PCBs
⚙️ Positioning in the semiconductor value chain and key verticals served
🚗 Cutting-edge solutions for yield improvement, precision, and counterfeit detection
🤝 Global partnerships with leaders like Nisene Technology Group
🏫 Collaboration with academia, startups, and the India Semiconductor Mission 🇮🇳
🧠 Future-ready tech like AI, 5G, and IoT—and how HCP balances R&D with market demand
👩🔬 Talent building, upskilling, and leadership lessons in a niche, high-impact industry
Discover what sets innovations like JetEtch® and Microwave Induced PlasmaEtch™ apart from global competitors, and hear real-world transformation stories from HCP’s clients. 🌟
Whether you're an engineer, policymaker, or startup dreamer, this episode is a blueprint for navigating and thriving in India's emerging semiconductor revolution. 💼🌐
🎯 Don’t miss the advice segment where our guest shares golden guidance for young entrepreneurs and semiconductor enthusiasts!
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Mr. Purushothaman Arumugam
Mr. Purushothaman Arumugam is the Managing Director and Founder of HCP Technologies Private Limited, bringing 15 years of leadership experience in the Sales and Marketing of Capital Equipment across industries such as Healthcare, Biotechnology, Electronics, Semiconductors, Solar, EV, Powder Metallurgy, and Gear Manufacturing. Over the years, he has built trusted partnerships with major private companies as well as prestigious government organizations, including DRDO, CSIR, ISRO, and leading academic institutes like IITs and NITs. His career has been driven by strong business acumen, a solution-oriented mindset, and a passion for helping clients succeed in an ever-evolving market.
In March 2024, Mr. Arumugam founded HCP Technologies — a company committed to transforming the Semiconductor, EV, and Electronics manufacturing landscape in India. HCP Technologies proudly supports global OEMs and operates with six core values at its foundation: Innovation, Quality, Customer Focus, Integrity, Collaboration, and Sustainability. With a clear vision and a relentless commitment to excellence, Mr. Arumugam is steering HCP Technologies to play a key role in building India's semiconductor future under the India Semiconductor Mission.
In this power-packed episode of The Semiconductor Podcast (TSP), we sit down with the dynamic founder of Augmatic Technologies, Mr. Surajit Datta, an emerging leader in India’s electronics design and manufacturing sector. 🇮🇳⚡ Mr. Datta shares his inspiring journey, invaluable experiences, and vision for the future. His insights reveal the strong sense of community and collaboration among business minds in Gujarat, where competition thrives through performance and collaboration in the workplace. What an incredible work culture!
🎧 Talking Points for the Episode with Augmatic Technologies
✨ The Beginning & Vision : Founding story, core mission, and early challenges.
🔩 Products & Services: Exploring the types of electronics developed, industries served, and the range of services offered in EMS, IoT, automation, and product development.
🧪 Innovation & Engineering Expertise: Highlighting the role of in-house R&D, IoT integration, and the company's key engineering strengths.
📡 Flagship Solutions & Custom Projects: Showcasing standout products like IoT Gateways and custom solutions tailored to client needs.
🧭 Client Engagement & Support: The journey from concept to delivery, including comprehensive documentation and after-sales support.
📏 Quality Assurance & Compliance: Ensuring excellence through rigorous testing, industry certifications, and quality practices.
🌱 Sustainability, Trends & Supply Chain: Adapting to trends, integrating eco-friendly practices, and maintaining supply chain resilience.
🔁 Feedback, Talent Development & Culture: How customer feedback fuels product improvements, and how the team is supported through training and a positive work culture.
⚙️ Industry Insights & Future Growth: Discussing challenges in the industry, upcoming innovations, and R&D collaborations shaping the future.
🌟 Distinctive Edge & Community Impact: What sets the company apart, their work in Gujarat, CSR initiatives, and advice for newcomers in the field.
Take a look at the facility : https://www.youtube.com/watch?v=wE56B5h3Qag
YT channel : https://www.youtube.com/@wittelb
IndiaMart Store : https://www.indiamart.com/augmatic-technologies/
✨ Tune in to discover what truly sets Augmatic Technologies apart and how they’re shaping the future of electronics—one product at a time.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Mr. Surajit Datta
Mr. Surajit Datta is a passionate professional with over 30 years of experience across various roles in mid-size and large enterprises, including Wipro Technologies, SITA Telecommunications, Reliance Communications, and Inferrix UK until 2019. In 2020, he founded Augmatic Technologies Pvt. Ltd., operating under the brand name WITTELB.
WittelB is an innovative and dynamic company specializing in Electronic Product Design, Engineering, and Electronics Manufacturing Services (EMC). With a state-of-the-art, fully automated SMT manufacturing facility and advanced equipment from leading global brands, WittelB provides unparalleled services in Electronics Manufacturing, Design & Engineering, Rapid Prototyping, New Product Design, and Supply Chain Management. The team brings extensive experience in electronics and IoT.
Based in Vadodara, Gujarat, WittelB contributes to the growing ESDM ecosystem in the state, aligning with the nation’s 'Make in India' initiative.
Mr. Datta holds a Bachelor’s degree in Electronics from Pune University (1993).
Core Strengths:
• Leadership and Team Management
• Technical Solution Design in M2M & IoT
• Electronics Product Design
• Wireless Communication Technologies
• Business Strategy and Operations
Certifications:
• Energy Auditor, Certified by BEE, Government of India
• Cisco Certified Network Professional (CCNP)
Watch the podcast here :
In this episode of The Semiconductor Podcast, we’re joined by a dynamic leader , Mr. Murugavel Ganesan , who has navigated the world of semiconductors through the halls of Intel and Infineon, and now leads the charge at SiliconAuto — a company shaping the future of automotive chip design and intelligent mobility 🚗⚙️.
This episode dives into a variety of thought-provoking topics:
- Industry 4.0 & AI-driven chip design: How these innovations are transforming the semiconductor landscape 🧠💡
- Building chips for EVs & autonomous vehicles vs. consumer gadgets: Exploring the technical and strategic challenges 🔍
- Autonomous driving: Is it a natural tech evolution or a societal necessity? 🛣️
- Startups thriving amidst semiconductor giants: How innovation and agility fuel success 🚀
- Global lessons: Insights from hubs like Taiwan, Germany, and the US, and how India can carve its niche in automotive semiconductors 🇮🇳
- Career guidance: For engineers stepping into product leadership roles and aspiring entrepreneurs venturing into deep tech 🧭
- Guest’s personal blog (https://blog.digitalelectronics.co.in) : Here
- His leadership philosophy: How he balance corporate leadership, mentoring, and ecosystem-building 🌐✍️
Whether you're a professional in the chip industry, a curious technologist, or a founder at the intersection of mobility and microelectronics, this episode offers rich insights, hard-earned lessons, and a compelling vision for the automotive semiconductor roadmap to 2035 and beyond 📅🔮.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Mr. Murugavel Ganesan
M. Murugavel Ganesan is currently the Product Director at SiliconAuto India. He is a seasoned semiconductor product and technical leader with extensive ASIC and SoC experience across the Automotive, Telecom, Wireless, Wireline, and IoT domains. With a well-rounded career spanning over 25 years, Murugavel has successfully managed complex programs at Intel and driven innovation at Infineon Technologies. He excels at navigating the intricacies of product definition, strategy, customer engagement, technical execution, and the integration of emerging and advanced semiconductor technologies.
A graduate of Texas A&M University, Murugavel is widely recognized for delivering innovative solutions with a strong emphasis on timeliness, quality, precise communication, and effective problem-solving strategies. His unwavering passion for technology, commitment to quality excellence, and the dynamic opportunities at SiliconAuto fuel his drive to lead the future of automotive innovation.
In this inspiring episode of The Semiconductor Podcast (TSP), we sit down with a dynamic young CEO who turned bold dreams into reality just after graduation! 🎓✨ We dive into his incredible journey—from early influences like his father sparking a love for electronics, to launching Zerovortex and KUE Link Technologies, two startups set to redefine education and electric mobility. 🚗⚡
We explore how ZV Community is revolutionizing learning through gamification, collaboration, and creativity, offering a fresh alternative to traditional education models. 🎮📚 Our guest shares the tech magic behind the platform, the delicate balance of competition and support, and the vision for empowering learners worldwide.
Switching gears to KUE Link Technologies, we discuss the critical gaps in the EV landscape that his company is addressing, the open-access innovation model, and the future trends poised to reshape electric mobility over the next decade. 🔋🌎
Throughout the conversation, he opens up about the highs and lows of entrepreneurship, the importance of mentorship, the impact of government policies, and key lessons from the cutting-edge worlds of RISC-V and IoT. 🛠️🌐
Whether you're an aspiring entrepreneur, an educator, a tech enthusiast, or someone passionate about sustainability, this episode is packed with insights, real-world advice, and a whole lot of inspiration. 🚀💬
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : CH Akshar
CH Akshar is the founder of Kue Link Technology and the visionary behind the Zerovortex Community. With a background in Electronics and Communication Engineering, he began his journey into the electric vehicle (EV) space during his B.Tech years by launching Kue Link as a research-focused initiative to explore the EV ecosystem and its market landscape. Over time, this endeavor has evolved into the development of a modular, future-proof electric vehicle platform, designed for adaptability and long-term innovation.
Akshar is a passionate experimenter and hands-on hardware enthusiast. His curiosity drives him to explore everything from the latest development boards and single-board computers to designing and analyzing custom hardware architectures. He thrives on pushing the boundaries of what’s possible in the hardware space.
At the heart of his work is a deep belief in the power of networking and cross-industry collaboration. Akshar sees true innovation emerging not just from isolated effort, but through active engagement, knowledge sharing, and community building. He also enjoys studying innovation through business and technology case studies, uncovering how ideas take shape across different domains.
Frustrated by the gap between theoretical knowledge and its practical application, Akshar founded the Zerovortex Community—a platform dedicated to deep learning, hands-on building, and interdisciplinary experimentation. His vision is to cultivate a culture where learning is immersive, collaborative, and constantly evolving.
In this episode, we explore Akshar’s journey, his hardware-first mindset, and his mission to build communities that transform the way we learn, innovate, and co-create.
What do you get when a PhD in physics swaps the lab coat for a journalist’s pen and a global stage in power electronics? You get Dr. Maurizio Di Paolo Emilio — and one of the most fascinating episodes we’ve ever gone through.
In this powerful electrifying conversation, we explore
⚡ What pulled him from academia into the heart of the GaN and SiC game changers
📚 Why he had to write not one, but two separate books on these breakthrough materials
🧠 How power electronics is quietly fueling AI, edge computing, smart grids, and the IoT
🔥 The real-world wins where GaN and SiC leave traditional silicon in the dust
💡 His unexpected hobby, his dream time-travel conversation, and advice for the next generation of power players
And yes — he’s the first power electronics expert ever on the show.
Dr. Maurizio doesn’t just talk about tech. He talks about vision. About gaps that needed filling. About turning sparks of curiosity into chapters, careers, and global impact.
This isn’t just an episode. It’s a roadmap to what’s next in power.
🎧 Listen in and find out where the future of electronics is really headed — and how you can be part of it.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape.
Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Dr. Maurizio Di Paolo Emilio
Maurizio Di Paolo Emilio is editor-in-chief of Power Electronics News and embedded.com, as well as an EE Times correspondent. He holds a Ph. D. in Physics and is a Telecommunications Engineer. He has worked on various international projects in the field of gravitational waves research, designing a thermal compensation system (TCS) and data acquisition and control systems, and on others about x-ray microbeams in collaboration with Columbia University, high voltage systems and space technologies for communications and motor control with ESA/INFN. TCS has been applied to the Virgo and LIGO experiments, which detected gravitational waves for the first time and earned the Nobel Prize in 2017. Since 2007, he has been a reviewer for scientific publications for academics such as Microelectronics Journal and IEEE journals. Moreover, he has collaborated with different electronic industry companies and several Italian and English blogs and magazines, such as Electronics World, Elektor, Mouser, Automazione Industriale, Electronic Design, All About Circuits, Fare Elettronica, Elettronica Oggi, and PCB Magazine, as a technical writer/editor, specializing in several topics of electronics and technology. From 2015 to 2018, he was the editor-in-chief of Firmware and Elettronica Open Source, which are technical blogs and magazines for the electronics industry. He participated in many conferences as a speaker of keynotes for different topics such as x-ray, space technologies, and power supplies. Maurizio enjoys writing and telling stories about Power Electronics, Wide Bandgap Semiconductors, Automotive, IoT, Embedded, Energy, and Quantum Computing. Maurizio has been an AspenCore content editor since 2019. He is currently editor-in-chief of Power Electronics News and Embedded, and a correspondent for EE Times. He is the host of PowerUP, a podcast about power electronics, and the promoter and organizer of the PowerUP Virtual Conference, a summit where each year great speakers talk about the power electronics design trends. Moreover, he has contributed to a number of technical and scientific articles as well as a couple of Springer books on energy harvesting and data acquisition and control systems.
Useful Links (provided by our Guest) As we have discussed in the Podcast :
https://link.springer.com/book/10.1007/978-3-031-63238-9
https://link.springer.com/book/10.1007/978-3-031-63418-5
https://www.powerelectronicsnews.com/10-things-to-know-about-gan/
https://www.powerelectronicsnews.com/10-things-to-know-about-sic/
https://www.powerelectronicsnews.com/
It’s not every day that you get to speak with the founder and chief investigator of a MEITY Centre of Excellence — on The Semiconductor Podcast, we had the rare privilege.
We were joined by Prof. Bijoy Krishna Das from IIT Madras🇮🇳, a pioneer in Programmable Silicon Photonics — one of the most exciting frontiers in cutting-edge technology today.
For the past 19 years, Prof. Das has been tirelessly working to establish a visionary “Product–Research–Development–Manufacturing” model in India. What makes his journey even more remarkable is his industry collaboration philosophy — working with mainstream players on an equal knowledge-sharing basis.
With a team of diligent researchers and an unwavering commitment, Prof. Das is well on his way to making CPPICS a global trendsetter.
As India dives deeper into the era of tech innovation, let’s take a moment to celebrate such contributions to the Make in India movement. 🇮🇳
From his early journey in photonics to building one of India’s most advanced research hubs, Prof. Das shares how he's bringing to life a powerful “Product–Research–Development–Manufacturing” model 💡🏭 — right here in India.
✨ What’s Inside This Episode?
🔹 How Programmable Photonic ICs work — explained in simple terms 🧠
🔹 Real-world use cases and the promise of Silicon Photonics 🌐
🔹 The origin and goals of CPPICS — aligned with MeitY’s national vision 🎯
🔹 Cutting-edge research in Quantum Photonics, Microwave Photonics, and more ⚛️📡
🔹 Collaborations with iZMO Microsystems, SilTerra, and international labs 🤝🌍
🔹 Training, education, and skilling for students and researchers 🎓📘
🔹 CPPICS’s strides toward scalability, sustainability, and commercialization ♻️💼
🔹 Success stories, patents, and a roadmap to making India a global photonics leader 🏆🌟
🔹 A message of inspiration for young tech minds and innovators 🙌👩🔬👨🔬
🎙️ Whether you're a student, researcher, startup founder, or tech enthusiast, this episode is your front-row seat to India’s photonics revolution.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest :Professor Bijoy Krishna Das
Prof. Dr. Bijoy Krishna Das joined the Department of Electrical Engineering at IIT Madras as an Assistant Professor in 2006 and has since pioneered the development of silicon photonics research in India. At a time when IMEC Belgium had just initiated Silicon Photonics MPW runs with limited PDK offerings, he laid the groundwork for indigenous technology development, establishing in-house capabilities in silicon photonics design, fabrication, and characterization. His vision was to expose Indian students and researchers to CMOS-compatible silicon photonics, enabling them to make impactful contributions at a time when core engineering opportunities were scarce. Over the years, he has mentored seven Ph.D. scholars, fifteen MS (by research) students, and guided over 25 BTech/MTech projects, many of whom are now contributing to advanced semiconductor R&D globally. His leadership led to the establishment of India’s first Silicon Photonics Centre of Excellence—CPPICS—at IIT Madras, supported by MeitY, and he is also a founding member of the Centre for NEMS and Nanophotonics (CNNP). Currently, he leads a vibrant research group under the mission "Silicon Photonics Enabled Quantum Photonic Integrated Circuits and Systems (SPEQCS)," mentoring a team of postdoctoral researchers and scholars dedicated to advancing quantum photonic technologies.
In this article, we have provided an in-depth discussion on specialized routing in VLSI Physical Design, covering several key concepts and techniques essential to advanced chip design. We begin by outlining the overall design flow and introducing the role of specialized routing in enhancing performance and efficiency. The discussion includes detailed insights into area routing, focusing on its primary objectives and the various optimization factors involved. We then explore the fundamentals of clock networks, examining delay issues, clock skew, and common routing challenges. Additionally, we present a multi-part analysis of modern clock tree synthesis techniques, comparing methods like MMM and RGM, and concluding with strategies for optimizing clock skew and managing power trade-offs in complex VLSI systems.
Design Flow & Specialized Routing :
In digital integrated circuits, signal wires undergo global routing first followed by detailed routing. However, in certain designs—such as analog circuits and printed circuit boards (PCBs) with gridless (trackless) routing—this distinction is unnecessary. Similarly, older or smaller designs with only one or two metal layers also fall into this category. When global and detailed routing are not handled separately, area routing is used to directly establish metal connections for signal routing. Unlike routing with multiple metal layers, area routing prioritizes minimizing wire crossings. Clock signals require special considerations.
Area Routing :
Objective: Area routing aims to connect all nets while, bypassing global routing, operating within the available layout, pace, adhering to geometric and electrical constraints.
Optimization Goals: Minimize total routed length and number of vias, optimize wiring area and routing layers used, reduce circuit delay while maintaining uniform wire density, lower capacitive coupling between adjacent routes.
Constraints Considered: Technological constraints like number of routing layers, wire width, electrical constraints like signal integrity, coupling effects, geometric constraints like preferred routing directions, wire pitch etc.
Impact of Net Ordering:
- The sequence of net routing affects efficiency and runtime.
- Greedy wire-length-based routing can cause inefficiencies.
- Multi-pin nets require careful decomposition and ordering.
Net and Pin Ordering Strategies:
1. Pin Ordering: Use Steiner tree-based algorithms to convert multi-pin nets into 2pin nets. Sort pin locations by x coordinate and connect from left to right using shortest-
path algorithms.
2. Net Ordering Challenges: Finding the optimal net order is complex (n! Possibilities).
Net Ordering Rules: Nets with larger aspect ratios are routed first. If AR is the same, the shorter net length is prioritized. If a net’s pins are fully inside another net’s bounding box, it is routed first. The net with fewer interfering pins in its bounding box is routed first. Ties are resolved based on total pin count inside the bounding box.
Basic Concepts in Clock Networks:
Most digital designs are synchronous, i.e.,computations
occur in sync with a clock signal . The clock ensures that internal state variables and inputs are processed correctly through combinational logic, generating new outputs and state updates. The clock signal, often called the system’s heartbeat, can be generated off-chip or by on-chip analog circuits like PLLs/DLLs. Its frequency may be divided or multiplied depending on the needs of different circuit
blocks. Clock tree routing is used to distribute the clock signal efficiently. It builds a clock tree for each clock domain, ensuring that the signal reaches all flip-flops and latches (sinks) at the same time. Unlike other routing types , clock routing focuses on minimizing skew so that all parts of the circuit receive the clock simultaneously.
A clock routing problem involves connecting ( n+1) terminals .
A clock routing solution consists of wire segments that connect all terminals, ensuring the signal from the source reaches every sink.
This solution has two key aspects:
i. Clock tree topology
ii. Embedding
Clock tree topology: A rooted binary tree G with n leaves representing the sinks.
Internal nodes include the source and any additional Steiner points.
Embedding: Defines the exact physical placement of the edges and internal nodes in the topology. Fig.a illustrates a six-sink clock tree instance, Fig. b shows its connection topology, and Fig. c presents a possible embedded clock tree solution.
Delay in Clock Networks:
Signal delay is the time a signal takes to switch states (low to high or high to low) as it travels through a routing tree. It
starts at logic gate outputs, built from nonlinear transistors, and moves through wires and vias, which add parasitic
effects. Exact delay calculations are complex, so tools like SPICE or PrimeTime are used for precise "signoff delay"
measurements. However, place-and-route algorithms use approximate models, such as the linear and Elmore delay
models.
Linear Delay Model : In the linear delay model, signal delay between nodes i and j is proportional to the path length in the
routing tree, independent of connection topology. The normalized linear delay between nodes u and w is the sum of edge lengths along the path. On-chip wires have both resistance (R) and capacitance (C), which increase with length. Due to RC effects, wire delay grows quadratically, which the linear model does not capture. Despite this, it remains useful in design tools, especially for older technologies with lower drive resistance and wider wires. Its simplicity makes it widely used in EDA software.
Elmore Delay Model : The Elmore delay model provides a
more accurate delay estimate by considering resistances
and capacitances in the routing tree, especially for modern
circuits with significant RC effects. Physical design tools
use the Elmore delay approximation for three key reasons.
First, it considers the effect of off-path wire capacitance on
sink delay. Second, it provides a good balance of accuracy
and correlation with circuit simulator estimates. Third, it can
be computed efficiently in linear time using two depth-first
traversals—one to determine capacitance below each node
and another to calculate delays from the source to each
node.
Clock Skew :
Clock Skew : This is the maximum difference in clock signal arrival times between sinks. Since the clock signal should reach all sinks simultaneously, minimizing skew is crucial
for circuit timing.
Local skew : The maximum difference in clock arrival times between related sinks (sinks that are sequentially adjacent, meaning there is a combinational logic path between them).
Global skew : The maximum difference in clock arrival times between any two sinks, whether related or not. It is the difference between the shortest and longest source-to-sink
path delays in the clock tree. In most cases, global skew is what is referred to as "clock skew" in design analysis.
Clock Routing Problems:
There are few clock routing problems. Modern low-power clock network design integrates zero-skew trees and relies on SPICE for accurate circuit simulation.
Zero-Skew Tree (ZST) Problem : A ZST ensures that the clock signal reaches all sinks at
the same time. Skew is defined using a delay estimate like linear or Elmore delay.
Bounded-Skew Tree (BST) Problem : While ZSTs are useful in theory, exact zero skew is not practical due to, increased wirelength, leading to higher capacitance and manufacturing variations, which cause differences in wire resistance and capacitance. Instead, real-world clock trees allow a small skew within a given bound.
Useful-Skew Tree Problem : In some cases, global skew control is unnecessary. Instead, the focus is on local skew between related flip-flops or latches. Enforcing strict global skew constraints can over complicate the problem.
Fishburn proposed a useful-skew method, where clock arrival times at sinks are intentionally adjusted to minimize the clock period, maximize the timing margin. This approach helps ensure that data signals between flip-flops arrive neither too late (zero clocking) nor too early (double clocking). By optimizing sink arrival times, the clock period P) can be reduced, improving circuit performance.
Modern Clock Tree Synthesis
Clock trees are crucial in synchronous circuit design, affecting both performance and power consumption. A well-designed
clock tree ensures low skew, delivering the clock signal to all sequential gates simultaneously. After the initial tree
construction the clock tree goes through, Clock buffer insertion to strengthen the signal, Skew optimization to further
reduce timing variations.
Constructing Trees with Zero Global Skew :
Five early clock tree construction algorithms, whose core ideas still influence modern EDA tools. These algorithms address different scenarios:
1. Builds a clock tree without considering exact sink positions.
2. Constructs both the tree structure and physical layout simultaneously.
3. Given a predefined topology, determines its physical
placement.
1. H-Tree :
The H-tree is a self-similar fractal structure that ensures exact zero skew due to its symmetry. It is built by recursively dividing a unit square :
- A central segment is placed through the root.
- Two shorter perpendicular segments extend to the centers of four quadrants.
- This process continues until reaching all sinks.
The H-tree is widely used for top-level clock distribution, but it has limitations:
1. Blockages can disrupt the pattern.
2. Irregular sink placement makes direct implementation difficult.
3. High routing cost.
To reduce signal reflections, wire tapering is used, where the width halves at each branching point.
2. Method of Means and Medians (MMM) :
The MMM algorithm, proposed by Jackson, Srinivasan, and Kuh in 1990 , improves on the H-tree by handling arbitrarily placed sinks. It follows a recursive approach:
1. Partition terminals into two equal subsets based on the median.
2. Connect the center of mass of the whole set to the centers of mass of
both subsets (mean).
This method is flexible and adapts to different sink distributions. While
MMM can be simplified into an H-tree-like approach, it only minimizes
skew heuristically. In the worst case, the longest source-to-sink path can
be as large as the chip diameter, making the algorithm's effectiveness
highly dependent on cut direction selection.
3. Recursive Geometric Matching (RGM) :
The RGM algorithm, introduced in 1991, is a bottom-up approach to clock tree construction, unlike the top-down MMM algorithm.
How RGM Works :
The algorithm finds a minimum-cost geometric matching of n/2 line segments, ensuring no two segments share an endpoint while minimizing total segment length. After matching, a balance or tapping point is placed on each segment to maintain zero skew between connected sinks. The n/2 tapping points from one stage serve as inputs
for the next matching step. The process continues until the clock tree is fully constructed.
MMM vs. RGM :
RGM improves clock tree balance and reduces wirelength compared to MMM. Above figure compares MMM and RGM for four sinks. If MMM selects a poor cut direction, RGM can cut wirelength in half. However, like MMM, RGM does not ensure zero skew. If two subtrees have very different delays and their roots are matched, finding a zero-skew tapping point may not be possible.
4. Exact Zero Skew Algorithm :
Proposed in 1991, the Exact Zero Skew Algorithm improves upon RGM by ensuring precise skew balancing using the Elmore delay model instead of the simpler linear delay model.
Key Feature : It calculates exact zero-skew tapping points using the Elmore delay model, leading to lower actual clock skew in real designs. When merging two sub-trees with different source-sink delays, it adjusts wire lengths to equalize the delays. During merging, the zero- skew tapping point is carefully placed along the matched segment.
5. Deferred-Merge Embedding :
The DME algorithm improves clock tree construction by delaying the selection of merging (tapping) points for
subtrees. Unlike earlier methods that fix internal node locations early, DME optimally places these nodes later, ensuring, minimal source-to- sink delay and minimal total tree cost.
How DME Works : Unlike MMM and RGM, which only require a set of sink locations, DME needs a predefined tree topology as input.
Key Advantage : MMM, RGM,Exact Zero Skew fix internal node positions too early, limiting flexibility. DME ensures more optimal placement of internal nodes, leading to better clock tree performance.
Clock Skew Optimization & Power Trade-off :
Key Challenges: Low clock skew is critical for high-performance designs. Clock networks consume significant power, requiring trade-offs between skew and capacitance. Accurate timing analysis is needed, although simulations are time-consuming. Closed-form delay models are inaccurate. A common approach is to optimize using Elmore delay model and then fine-tune with more accurate models.
Clock Tree Optimization Steps:
Clock Tree optimization includes ,
1.Geometric clock tree construction,
2. Initial clock buffer insertion,
3. Clock buffer sizing,
4. Wire sizing,
5. Wire snaking.
These steps account for PVT variations.
High-Level Skew Optimization:
- Earlier, a single buffer could drive the clock tree.
- With technology scaling, multiple buffers are required.
- Buffer insertion ensures the clock signal reaches all sinks efficiently.
- Ginneken's algorithm optimally buffers a tree to minimize Elmore delay:
- Runs in O(n²) time, where n is the number of buffer locations. A faster O(n log
n) variant improves scalability. Optimizations reduce skew, power consumption, and variability effects.
Clock Buffer Sizing:
- Initial buffer sizes impact later optimizations.
- Best size is determined experimentally (e.g., binary search).
- To fix skew between two sinks s₁ and s₂:
- Identify the unique path (ʌ) between them.
- Upsize buffers based on precomputed tables.
- Larger buffers improve robustness but increase power and delay.
Wire Sizing:
- Wire width affects power and manufacturing variation. Wider wires are m ore resilient to variation, although the
capacitance and power consumption both are higher. Thinner wires are used in low-power designs, Wire width can be
adjusted dynamically based on timing analysis.
Low-Level Skew Optimization:
- Focuses on local adjustments with higher precision.
- Techniques: Wire sizing i.e , adjust widths for fine-tuned timing, wire snaking i.e, increase path length to delay fast
signals, wire detouring increases capacitance & resistance, slowing propagation.
Variation Modeling:
- Process variations impact each transistor differently.
- Environmental factors (e.g., temperature, voltage fluctuations)
affect performance.
- Two modeling approaches:
1. Monte Carlo simulations, accurate but slow.
2. Precomputed lookup tables, efficient and reusable
- Captures worst-case skew variations based on:
- Technology node, buffer/wire library, path length, variation model, yield.
- Enables fast, accurate optimizations (e.g., buffer sizing).
Advanced Clocking Techniques:
Active deskewing & clock meshes (common in CPUs). Clock gating (reduces power dissipation).
