What do you get when a PhD in physics swaps the lab coat for a journalist’s pen and a global stage in power electronics? You get Dr. Maurizio Di Paolo Emilio — and one of the most fascinating episodes we’ve ever gone through.
In this powerful electrifying conversation, we explore
⚡ What pulled him from academia into the heart of the GaN and SiC game changers
📚 Why he had to write not one, but two separate books on these breakthrough materials
🧠 How power electronics is quietly fueling AI, edge computing, smart grids, and the IoT
🔥 The real-world wins where GaN and SiC leave traditional silicon in the dust
💡 His unexpected hobby, his dream time-travel conversation, and advice for the next generation of power players
And yes — he’s the first power electronics expert ever on the show.
Dr. Maurizio doesn’t just talk about tech. He talks about vision. About gaps that needed filling. About turning sparks of curiosity into chapters, careers, and global impact.
This isn’t just an episode. It’s a roadmap to what’s next in power.
🎧 Listen in and find out where the future of electronics is really headed — and how you can be part of it.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape.
Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Dr. Maurizio Di Paolo Emilio
Maurizio Di Paolo Emilio is editor-in-chief of Power Electronics News and embedded.com, as well as an EE Times correspondent. He holds a Ph. D. in Physics and is a Telecommunications Engineer. He has worked on various international projects in the field of gravitational waves research, designing a thermal compensation system (TCS) and data acquisition and control systems, and on others about x-ray microbeams in collaboration with Columbia University, high voltage systems and space technologies for communications and motor control with ESA/INFN. TCS has been applied to the Virgo and LIGO experiments, which detected gravitational waves for the first time and earned the Nobel Prize in 2017. Since 2007, he has been a reviewer for scientific publications for academics such as Microelectronics Journal and IEEE journals. Moreover, he has collaborated with different electronic industry companies and several Italian and English blogs and magazines, such as Electronics World, Elektor, Mouser, Automazione Industriale, Electronic Design, All About Circuits, Fare Elettronica, Elettronica Oggi, and PCB Magazine, as a technical writer/editor, specializing in several topics of electronics and technology. From 2015 to 2018, he was the editor-in-chief of Firmware and Elettronica Open Source, which are technical blogs and magazines for the electronics industry. He participated in many conferences as a speaker of keynotes for different topics such as x-ray, space technologies, and power supplies. Maurizio enjoys writing and telling stories about Power Electronics, Wide Bandgap Semiconductors, Automotive, IoT, Embedded, Energy, and Quantum Computing. Maurizio has been an AspenCore content editor since 2019. He is currently editor-in-chief of Power Electronics News and Embedded, and a correspondent for EE Times. He is the host of PowerUP, a podcast about power electronics, and the promoter and organizer of the PowerUP Virtual Conference, a summit where each year great speakers talk about the power electronics design trends. Moreover, he has contributed to a number of technical and scientific articles as well as a couple of Springer books on energy harvesting and data acquisition and control systems.
Useful Links (provided by our Guest) As we have discussed in the Podcast :
https://link.springer.com/book/10.1007/978-3-031-63238-9
https://link.springer.com/book/10.1007/978-3-031-63418-5
https://www.powerelectronicsnews.com/10-things-to-know-about-gan/
https://www.powerelectronicsnews.com/10-things-to-know-about-sic/
https://www.powerelectronicsnews.com/
It’s not every day that you get to speak with the founder and chief investigator of a MEITY Centre of Excellence — on The Semiconductor Podcast, we had the rare privilege.
We were joined by Prof. Bijoy Krishna Das from IIT Madras🇮🇳, a pioneer in Programmable Silicon Photonics — one of the most exciting frontiers in cutting-edge technology today.
For the past 19 years, Prof. Das has been tirelessly working to establish a visionary “Product–Research–Development–Manufacturing” model in India. What makes his journey even more remarkable is his industry collaboration philosophy — working with mainstream players on an equal knowledge-sharing basis.
With a team of diligent researchers and an unwavering commitment, Prof. Das is well on his way to making CPPICS a global trendsetter.
As India dives deeper into the era of tech innovation, let’s take a moment to celebrate such contributions to the Make in India movement. 🇮🇳
From his early journey in photonics to building one of India’s most advanced research hubs, Prof. Das shares how he's bringing to life a powerful “Product–Research–Development–Manufacturing” model 💡🏭 — right here in India.
✨ What’s Inside This Episode?
🔹 How Programmable Photonic ICs work — explained in simple terms 🧠
🔹 Real-world use cases and the promise of Silicon Photonics 🌐
🔹 The origin and goals of CPPICS — aligned with MeitY’s national vision 🎯
🔹 Cutting-edge research in Quantum Photonics, Microwave Photonics, and more ⚛️📡
🔹 Collaborations with iZMO Microsystems, SilTerra, and international labs 🤝🌍
🔹 Training, education, and skilling for students and researchers 🎓📘
🔹 CPPICS’s strides toward scalability, sustainability, and commercialization ♻️💼
🔹 Success stories, patents, and a roadmap to making India a global photonics leader 🏆🌟
🔹 A message of inspiration for young tech minds and innovators 🙌👩🔬👨🔬
🎙️ Whether you're a student, researcher, startup founder, or tech enthusiast, this episode is your front-row seat to India’s photonics revolution.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest :Professor Bijoy Krishna Das
Prof. Dr. Bijoy Krishna Das joined the Department of Electrical Engineering at IIT Madras as an Assistant Professor in 2006 and has since pioneered the development of silicon photonics research in India. At a time when IMEC Belgium had just initiated Silicon Photonics MPW runs with limited PDK offerings, he laid the groundwork for indigenous technology development, establishing in-house capabilities in silicon photonics design, fabrication, and characterization. His vision was to expose Indian students and researchers to CMOS-compatible silicon photonics, enabling them to make impactful contributions at a time when core engineering opportunities were scarce. Over the years, he has mentored seven Ph.D. scholars, fifteen MS (by research) students, and guided over 25 BTech/MTech projects, many of whom are now contributing to advanced semiconductor R&D globally. His leadership led to the establishment of India’s first Silicon Photonics Centre of Excellence—CPPICS—at IIT Madras, supported by MeitY, and he is also a founding member of the Centre for NEMS and Nanophotonics (CNNP). Currently, he leads a vibrant research group under the mission "Silicon Photonics Enabled Quantum Photonic Integrated Circuits and Systems (SPEQCS)," mentoring a team of postdoctoral researchers and scholars dedicated to advancing quantum photonic technologies.
In this article, we have provided an in-depth discussion on specialized routing in VLSI Physical Design, covering several key concepts and techniques essential to advanced chip design. We begin by outlining the overall design flow and introducing the role of specialized routing in enhancing performance and efficiency. The discussion includes detailed insights into area routing, focusing on its primary objectives and the various optimization factors involved. We then explore the fundamentals of clock networks, examining delay issues, clock skew, and common routing challenges. Additionally, we present a multi-part analysis of modern clock tree synthesis techniques, comparing methods like MMM and RGM, and concluding with strategies for optimizing clock skew and managing power trade-offs in complex VLSI systems.
Design Flow & Specialized Routing :
In digital integrated circuits, signal wires undergo global routing first followed by detailed routing. However, in certain designs—such as analog circuits and printed circuit boards (PCBs) with gridless (trackless) routing—this distinction is unnecessary. Similarly, older or smaller designs with only one or two metal layers also fall into this category. When global and detailed routing are not handled separately, area routing is used to directly establish metal connections for signal routing. Unlike routing with multiple metal layers, area routing prioritizes minimizing wire crossings. Clock signals require special considerations.
Area Routing :
Objective: Area routing aims to connect all nets while, bypassing global routing, operating within the available layout, pace, adhering to geometric and electrical constraints.
Optimization Goals: Minimize total routed length and number of vias, optimize wiring area and routing layers used, reduce circuit delay while maintaining uniform wire density, lower capacitive coupling between adjacent routes.
Constraints Considered: Technological constraints like number of routing layers, wire width, electrical constraints like signal integrity, coupling effects, geometric constraints like preferred routing directions, wire pitch etc.
Impact of Net Ordering:
- The sequence of net routing affects efficiency and runtime.
- Greedy wire-length-based routing can cause inefficiencies.
- Multi-pin nets require careful decomposition and ordering.
Net and Pin Ordering Strategies:
1. Pin Ordering: Use Steiner tree-based algorithms to convert multi-pin nets into 2pin nets. Sort pin locations by x coordinate and connect from left to right using shortest-
path algorithms.
2. Net Ordering Challenges: Finding the optimal net order is complex (n! Possibilities).
Net Ordering Rules: Nets with larger aspect ratios are routed first. If AR is the same, the shorter net length is prioritized. If a net’s pins are fully inside another net’s bounding box, it is routed first. The net with fewer interfering pins in its bounding box is routed first. Ties are resolved based on total pin count inside the bounding box.
Basic Concepts in Clock Networks:
Most digital designs are synchronous, i.e.,computations
occur in sync with a clock signal . The clock ensures that internal state variables and inputs are processed correctly through combinational logic, generating new outputs and state updates. The clock signal, often called the system’s heartbeat, can be generated off-chip or by on-chip analog circuits like PLLs/DLLs. Its frequency may be divided or multiplied depending on the needs of different circuit
blocks. Clock tree routing is used to distribute the clock signal efficiently. It builds a clock tree for each clock domain, ensuring that the signal reaches all flip-flops and latches (sinks) at the same time. Unlike other routing types , clock routing focuses on minimizing skew so that all parts of the circuit receive the clock simultaneously.
A clock routing problem involves connecting ( n+1) terminals .
A clock routing solution consists of wire segments that connect all terminals, ensuring the signal from the source reaches every sink.
This solution has two key aspects:
i. Clock tree topology
ii. Embedding
Clock tree topology: A rooted binary tree G with n leaves representing the sinks.
Internal nodes include the source and any additional Steiner points.
Embedding: Defines the exact physical placement of the edges and internal nodes in the topology. Fig.a illustrates a six-sink clock tree instance, Fig. b shows its connection topology, and Fig. c presents a possible embedded clock tree solution.
Delay in Clock Networks:
Signal delay is the time a signal takes to switch states (low to high or high to low) as it travels through a routing tree. It
starts at logic gate outputs, built from nonlinear transistors, and moves through wires and vias, which add parasitic
effects. Exact delay calculations are complex, so tools like SPICE or PrimeTime are used for precise "signoff delay"
measurements. However, place-and-route algorithms use approximate models, such as the linear and Elmore delay
models.
Linear Delay Model : In the linear delay model, signal delay between nodes i and j is proportional to the path length in the
routing tree, independent of connection topology. The normalized linear delay between nodes u and w is the sum of edge lengths along the path. On-chip wires have both resistance (R) and capacitance (C), which increase with length. Due to RC effects, wire delay grows quadratically, which the linear model does not capture. Despite this, it remains useful in design tools, especially for older technologies with lower drive resistance and wider wires. Its simplicity makes it widely used in EDA software.
Elmore Delay Model : The Elmore delay model provides a
more accurate delay estimate by considering resistances
and capacitances in the routing tree, especially for modern
circuits with significant RC effects. Physical design tools
use the Elmore delay approximation for three key reasons.
First, it considers the effect of off-path wire capacitance on
sink delay. Second, it provides a good balance of accuracy
and correlation with circuit simulator estimates. Third, it can
be computed efficiently in linear time using two depth-first
traversals—one to determine capacitance below each node
and another to calculate delays from the source to each
node.
Clock Skew :
Clock Skew : This is the maximum difference in clock signal arrival times between sinks. Since the clock signal should reach all sinks simultaneously, minimizing skew is crucial
for circuit timing.
Local skew : The maximum difference in clock arrival times between related sinks (sinks that are sequentially adjacent, meaning there is a combinational logic path between them).
Global skew : The maximum difference in clock arrival times between any two sinks, whether related or not. It is the difference between the shortest and longest source-to-sink
path delays in the clock tree. In most cases, global skew is what is referred to as "clock skew" in design analysis.
Clock Routing Problems:
There are few clock routing problems. Modern low-power clock network design integrates zero-skew trees and relies on SPICE for accurate circuit simulation.
Zero-Skew Tree (ZST) Problem : A ZST ensures that the clock signal reaches all sinks at
the same time. Skew is defined using a delay estimate like linear or Elmore delay.
Bounded-Skew Tree (BST) Problem : While ZSTs are useful in theory, exact zero skew is not practical due to, increased wirelength, leading to higher capacitance and manufacturing variations, which cause differences in wire resistance and capacitance. Instead, real-world clock trees allow a small skew within a given bound.
Useful-Skew Tree Problem : In some cases, global skew control is unnecessary. Instead, the focus is on local skew between related flip-flops or latches. Enforcing strict global skew constraints can over complicate the problem.
Fishburn proposed a useful-skew method, where clock arrival times at sinks are intentionally adjusted to minimize the clock period, maximize the timing margin. This approach helps ensure that data signals between flip-flops arrive neither too late (zero clocking) nor too early (double clocking). By optimizing sink arrival times, the clock period P) can be reduced, improving circuit performance.
Modern Clock Tree Synthesis
Clock trees are crucial in synchronous circuit design, affecting both performance and power consumption. A well-designed
clock tree ensures low skew, delivering the clock signal to all sequential gates simultaneously. After the initial tree
construction the clock tree goes through, Clock buffer insertion to strengthen the signal, Skew optimization to further
reduce timing variations.
Constructing Trees with Zero Global Skew :
Five early clock tree construction algorithms, whose core ideas still influence modern EDA tools. These algorithms address different scenarios:
1. Builds a clock tree without considering exact sink positions.
2. Constructs both the tree structure and physical layout simultaneously.
3. Given a predefined topology, determines its physical
placement.
1. H-Tree :
The H-tree is a self-similar fractal structure that ensures exact zero skew due to its symmetry. It is built by recursively dividing a unit square :
- A central segment is placed through the root.
- Two shorter perpendicular segments extend to the centers of four quadrants.
- This process continues until reaching all sinks.
The H-tree is widely used for top-level clock distribution, but it has limitations:
1. Blockages can disrupt the pattern.
2. Irregular sink placement makes direct implementation difficult.
3. High routing cost.
To reduce signal reflections, wire tapering is used, where the width halves at each branching point.
2. Method of Means and Medians (MMM) :
The MMM algorithm, proposed by Jackson, Srinivasan, and Kuh in 1990 , improves on the H-tree by handling arbitrarily placed sinks. It follows a recursive approach:
1. Partition terminals into two equal subsets based on the median.
2. Connect the center of mass of the whole set to the centers of mass of
both subsets (mean).
This method is flexible and adapts to different sink distributions. While
MMM can be simplified into an H-tree-like approach, it only minimizes
skew heuristically. In the worst case, the longest source-to-sink path can
be as large as the chip diameter, making the algorithm's effectiveness
highly dependent on cut direction selection.
3. Recursive Geometric Matching (RGM) :
The RGM algorithm, introduced in 1991, is a bottom-up approach to clock tree construction, unlike the top-down MMM algorithm.
How RGM Works :
The algorithm finds a minimum-cost geometric matching of n/2 line segments, ensuring no two segments share an endpoint while minimizing total segment length. After matching, a balance or tapping point is placed on each segment to maintain zero skew between connected sinks. The n/2 tapping points from one stage serve as inputs
for the next matching step. The process continues until the clock tree is fully constructed.
MMM vs. RGM :
RGM improves clock tree balance and reduces wirelength compared to MMM. Above figure compares MMM and RGM for four sinks. If MMM selects a poor cut direction, RGM can cut wirelength in half. However, like MMM, RGM does not ensure zero skew. If two subtrees have very different delays and their roots are matched, finding a zero-skew tapping point may not be possible.
4. Exact Zero Skew Algorithm :
Proposed in 1991, the Exact Zero Skew Algorithm improves upon RGM by ensuring precise skew balancing using the Elmore delay model instead of the simpler linear delay model.
Key Feature : It calculates exact zero-skew tapping points using the Elmore delay model, leading to lower actual clock skew in real designs. When merging two sub-trees with different source-sink delays, it adjusts wire lengths to equalize the delays. During merging, the zero- skew tapping point is carefully placed along the matched segment.
5. Deferred-Merge Embedding :
The DME algorithm improves clock tree construction by delaying the selection of merging (tapping) points for
subtrees. Unlike earlier methods that fix internal node locations early, DME optimally places these nodes later, ensuring, minimal source-to- sink delay and minimal total tree cost.
How DME Works : Unlike MMM and RGM, which only require a set of sink locations, DME needs a predefined tree topology as input.
Key Advantage : MMM, RGM,Exact Zero Skew fix internal node positions too early, limiting flexibility. DME ensures more optimal placement of internal nodes, leading to better clock tree performance.
Clock Skew Optimization & Power Trade-off :
Key Challenges: Low clock skew is critical for high-performance designs. Clock networks consume significant power, requiring trade-offs between skew and capacitance. Accurate timing analysis is needed, although simulations are time-consuming. Closed-form delay models are inaccurate. A common approach is to optimize using Elmore delay model and then fine-tune with more accurate models.
Clock Tree Optimization Steps:
Clock Tree optimization includes ,
1.Geometric clock tree construction,
2. Initial clock buffer insertion,
3. Clock buffer sizing,
4. Wire sizing,
5. Wire snaking.
These steps account for PVT variations.
High-Level Skew Optimization:
- Earlier, a single buffer could drive the clock tree.
- With technology scaling, multiple buffers are required.
- Buffer insertion ensures the clock signal reaches all sinks efficiently.
- Ginneken's algorithm optimally buffers a tree to minimize Elmore delay:
- Runs in O(n²) time, where n is the number of buffer locations. A faster O(n log
n) variant improves scalability. Optimizations reduce skew, power consumption, and variability effects.
Clock Buffer Sizing:
- Initial buffer sizes impact later optimizations.
- Best size is determined experimentally (e.g., binary search).
- To fix skew between two sinks s₁ and s₂:
- Identify the unique path (ʌ) between them.
- Upsize buffers based on precomputed tables.
- Larger buffers improve robustness but increase power and delay.
Wire Sizing:
- Wire width affects power and manufacturing variation. Wider wires are m ore resilient to variation, although the
capacitance and power consumption both are higher. Thinner wires are used in low-power designs, Wire width can be
adjusted dynamically based on timing analysis.
Low-Level Skew Optimization:
- Focuses on local adjustments with higher precision.
- Techniques: Wire sizing i.e , adjust widths for fine-tuned timing, wire snaking i.e, increase path length to delay fast
signals, wire detouring increases capacitance & resistance, slowing propagation.
Variation Modeling:
- Process variations impact each transistor differently.
- Environmental factors (e.g., temperature, voltage fluctuations)
affect performance.
- Two modeling approaches:
1. Monte Carlo simulations, accurate but slow.
2. Precomputed lookup tables, efficient and reusable
- Captures worst-case skew variations based on:
- Technology node, buffer/wire library, path length, variation model, yield.
- Enables fast, accurate optimizations (e.g., buffer sizing).
Advanced Clocking Techniques:
Active deskewing & clock meshes (common in CPUs). Clock gating (reduces power dissipation).
In this power-packed episode of The Semiconductor Podcast, we sit down with the brilliant Mr. Arghajit, Director of the ASIC division at Juniper Networks, to explore his incredible journey and the cutting-edge world of networking ASICs 🧠🔧.
In this episode, we dive into:
🔍 His inspiring journey in semiconductors — from student to director
⚙️ Challenges faced in complex ASIC designs — and how he overcame them
📈 How the industry has evolved, and what's on the horizon in the next decade
🌐 How ASICs enhance networking performance and efficiency
🧠 The role of AI/ML in shaping ASIC design for networking and data centers
🧩 Emerging tech like chiplets and heterogeneous integration
🔥 Power optimization and thermal management challenges in high-performance chips
🌱 Juniper’s commitment to green energy and reduced carbon emissions
🇮🇳 India’s growing footprint in global ASIC design and manufacturing
🚀 Skills he looks for when hiring ASIC engineers
💬 Advice for startups and freshers entering the ASIC world in the age of AI
Whether you're a budding engineer, a startup founder, or a curious mind, this episode is packed with actionable insights and future-forward wisdom 💫.
🎧 Tune in now and get inspired by the visionary leading cutting-edge ASIC development from the City of Joy!
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape.
Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest :Arghajit Basu
Mr. Arghajit Basu has done BE from Jadavpur University in Electronics and telecommunication and Masters in VLSI from IIT Kanpur. He has more than 24 years of industry experience in various semiconductor companies, also co-author of multiple US patents. Currently he is a Director in ASIC division of Juniper Networks leading the team in Kolkata center.
Watch the podcast here :
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape.
Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.In this engaging episode of The Semiconductor Podcast, we’re joined by Claus Aasholm, a seasoned expert in semiconductor market research. Together, we delve deep into the critical role of market research in shaping the VLSI ecosystem and the broader semiconductor industry. 🎙️ Podcast Episode: 🚀 Unlocking the Power of Semiconductor Market Research with Claus Aasholm 🔬💡
🔍What to Expect:
1️⃣ 🌟 Claus Aasholm's inspiring journey into the world of semiconductors. 2️⃣ 📊 What is semiconductor market research? Why is it crucial for the VLSI ecosystem? 3️⃣ 📈 How market research drives strategic decisions in semiconductor companies. 4️⃣ 🔙 A look back: How has the semiconductor market evolved over the last decade? ⏳ 5️⃣ 📡 Key trends shaping the industry—especially in VLSI. 🌍 6️⃣ 🚀 Emerging technologies that will revolutionize the semiconductor landscape! 7️⃣ 💡 How market research fuels innovation in VLSI. 8️⃣ 🎓 Advice for freshers looking to kickstart a career in VLSI! 🏆 9️⃣ 🏢 How big companies thrive while smaller ones often face acquisitions. 🤝 🔟 🔮 Predictions: Which key sectors will VLSI impact the most in the next decade?
1️⃣1️⃣ 🔗 Where to find more about Claus Aasholm’s work + subscribe to their newsletter! 📩
✨ Whether you're an industry professional, a student, or just curious about semiconductors, this episode is packed with valuable insights & expert knowledge. Don’t miss it! 🎧🔥🔗 Don’t miss this episode if you’re passionate about semiconductors, VLSI, or market research.💡 Subscribe to The Semiconductor Podcast for more expert insights and discussions about the ever-evolving semiconductor industry!
