In this power-packed episode of The Semiconductor Podcast, we delve into the remarkable journey of Kishore M.M.C, Founder and CEO of Global Marketing Services (GMS) a pioneering force that has quietly enabled India’s access to world-class technologies across semiconductors, EV batteries, MEMS, photonics, and more. 🔬⚡🚗
Founded over 24 years ago, GMS has grown from a bold idea to a vital technology bridge between global innovators and Indian customers—serving academic institutions like IISc and DRDO, commercial fabs, startups, and research labs across the country. 🏛️🤝🌍
In this in-depth conversation, Mr. Kishore opens up about:
🔹 The origin story of GMS: what inspired him to start, and the early challenges in a pre-ISM India 🛠️
🔹 India’s electronics landscape in the early 2000s vs. today’s ecosystem shift driven by AI, EVs, and ISM 🌄➡️🚀
🔹 Diversification across domains—from semiconductors and LED to battery tech and MEMS sensors 🧠🔋
🔹 How GMS selects international partners and brings cutting-edge solutions to India at the right time ⏳📦
🔹 Strategic collaborations with academia and government—navigating the unique needs of researchers and fabs 📚🏭
🔹 Emerging tech Mr. Kishore is excited about: silicon carbide, photonics, quantum, and the AI hardware revolution 💡🧬
He also reflects on leadership values, long-term goals for GMS, and the role of companies like his in shaping India’s position in the global semiconductor supply chain by 2030. 🌐🇮🇳
Mr. Kishore shares how logistics, awareness gaps, and timing challenges can be transformed into opportunities when guided by the right mindset, strong networks, and deep local understanding.
💡 Whether you’re a deeptech enthusiast, semiconductor founder, or student dreaming of building something meaningful—this episode offers rare insights from a veteran who has stayed ahead of the curve for over two decades.
🎧 Tune in to discover how vision, persistence, and quiet execution can spark revolutions in India's growing semiconductor story.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Mr. MMC Kishore
Mr. MMC Kishore is a seasoned entrepreneur and business leader with over 30 years of experience in the technology and marketing industries. He is the Founder and CEO of Global Marketing Services (GMS), India — a company he established in January 2001, which has grown into a respected name in marketing solutions, known for its client-centric approach, innovative strategies, and strong organizational culture. Under his leadership, GMS has successfully executed numerous major projects, leveraging a well-built infrastructure and a dynamic team culture. His commitment to quality, consistency, and long-term partnerships has shaped GMS into a trusted provider across various sectors. Prior to founding GMS, Mr. Kishore served as a Sales Engineer at El Camino Technologies Pvt. Ltd. from 1994 to 2000, where he honed his skills in technical sales, customer engagement, and market development. He holds a Bachelor of Science (B.Sc.) in Instrumentation from Bangalore University (1989–1992) and completed his schooling at St. Paul's High School. With a career spanning over 24 years as a business owner and leader, Mr. Kishore continues to inspire through his strategic vision, operational excellence, and unwavering passion for growth and innovation.
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A free and open-source EDA tool (formerly Oscad/FreeEDA)
Integrated Simulation Cockpit Built on top of tools like KiCad, Ngspice, GHDL, OpenModelica, Verilator, and more
Supports the SkyWater SKY130 PDK
Released under the GNU GPL license
Why watch the video ?
Discover a cost-effective alternative to proprietary tools.
Learn circuit design, simulation, PCB layout, and mixed-signal analysis using open tools in a single GUI.
Perfect for students, educators, and SME/MSMEs aiming for self-reliant EDA workflows
🛠️ What Will Be Covered?
✅ Walkthrough of the eSim website, including download & installation steps
✅ Overview of the Spoken Tutorial (self-Paced-Learning) content related to eSim
✅ Live demo of eSim’s capabilities with simple example circuits
– LCR Circuit
– BJT Amplifier
– CMOS Inverter
✅ Hands-on view of schematic creation and waveform plotting
✅ Tailored content for academic users and learners
👥 Who Should Attend?
UG/PG Electronics Engineering Students (BSc/BTech/M.Sc/MTech/MS)
Faculty Members & Researchers
Lab Instructors & Technical Staff
Anyone seeking an open-source EDA solution
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URLs :
eSim HomepageeSim TeamFOSSEE InternshipsSpoken Tutorial HomepageApplications of Spoken Tutorials
In this landmark episode of The Semiconductor Podcast (TSP), we sit down with a rare visionary — a serial entrepreneur, patent holder, and esteemed faculty at IIT Kharagpur — who has seamlessly bridged the worlds of academic research, chip design, and startup leadership. 🧑🏫💼📈
🔍 What sparks a Ph.D. holder to become a founder?
⚙️ How does deep research translate into high-impact leadership and innovation?
🌏 And what will it take to turn Eastern India into the next big semiconductor hub?
From his early days at Intel, Texas Instruments, and SanDisk to founding Sankalp Semiconductors and now leading Aantaric Technologies, our guest walks us through:
• The milestones, patents, and turning points that shaped his journey 🛤️
• How to build and lead 100+ strong high-performance analog design teams 🔧🔥
• The real-world role of AI/ML in analog and mixed-signal design 🤖📊
• How engineers can transition from “desk job survival” to patent-worthy innovation 💡📝
• His personal playbook for spotting research-backed, commercially viable ideas 🎯
But this episode is more than just a founder’s story — it’s a blueprint for ecosystem building.
Hear his passionate take on:
• Why Kolkata and Eastern India can be the next design powerhouse 🌉📡
• How institutions like IIT KGP, ISI, JU, NIT Durgapur, IIEST, and others can collaborate to build a deep tech and semiconductor ecosystem in the region 🏛️🧬
• Current initiatives, startup incubations, and what’s still missing for real momentum 🚀
👩💻 Whether you’re a student, engineer, policymaker, or startup dreamer, this conversation is packed with insights on leadership, innovation, and India's semiconductor potential.
🎧 Tune in to discover how to go from job seeker to job creator, from researcher to founder — and from follower to pioneer in India’s chip revolution. 🇮🇳✨
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Dr. Prajit Nandi
Prajit Nandi is a distinguished faculty member in the Department of Electrical Engineering at the Indian Institute of Technology (IIT) Kharagpur. With over 20 years of extensive experience in semiconductor product development, he has held pivotal roles in renowned multinational companies such as Intel, SanDisk, and Texas Instruments.
He is a founding team member of Sankalp Semiconductor Pvt. Ltd. (now part of HCL Technologies), where he played a critical role in incubating the Analog Design Team from STEP, IIT Kharagpur. He also established and scaled Sankalp’s Kolkata Design Center, building a robust team of over 100 engineers. Under his leadership, the center built strong analog design verticals in Data Converters, Power Management, and Clocking Systems, successfully serving top-tier clients including Analog Devices, Cadence, Nuvoton, STMicroelectronics, Toshiba, and Texas Instruments.
Prajit has mentored and trained numerous engineers, many of whom are now contributing to leading semiconductor firms in India and around the world. He is currently associated with Texas Instruments, where he works in the High-Speed Data Converter Group of the Analog Signal Chain Business Unit, contributing to the development of world-class high-performance data converters. He holds the rare distinction of serving as Design Architect and Product Lead in both the Analog Power Products (Automotive) and Analog Signal Chain business units at TI.
His research interests lie in Wireline Communications and Signal Chain Design. He holds 8 US patents, and has published 4 journal papers and 4 conference papers. Additionally, he serves as a technical advisor to Aantaric Technologies Pvt. Ltd.
🔗 Prajit Nandi – Aantaric Technologies
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In this article, we have explored critical aspects of reliability and integrated circuit (IC) failure in VLSI systems, with a focus on understanding the root causes and mechanisms behind these failures. The discussion begins with the fundamentals of CMOS IC failure and delves into the properties of interconnect metals, including their crystal structures, which influence performance and longevity. We examine key reliability concerns such as electromigration, metal stress voiding, and their implications on metal interconnects, especially in the context of copper-based technologies covered in two detailed segments. The article also investigates the structure of gate oxides, common defect types, and their role in determining gate oxide reliability in MOS devices, presented through a two-part explanation. Finally, we analyze the mechanisms behind ultrathin oxide breakdown and broader oxide failure modes, providing a comprehensive overview of reliability challenges in advanced semiconductor devices.
Understanding CMOS IC Failure :
As semiconductor technology continues to scale down and performance demands rise, ensuring the reliability of materials used in integrated circuits (ICs) has become increasingly critical. IC failure is often the result of complex interactions between electrical, thermal, mechanical, and environmental stresses acting on the materials within a device. From the integrity of interconnect metals to the robustness of gate dielectrics, each material layer plays a vital role in determining the long-term functionality and durability of an IC. Failures can manifest as performance degradation, intermittent faults, or catastrophic breakdowns, impacting both product quality and life cycle. Understanding the key mechanisms that contribute to material-related failures—such as electromigration, dielectric breakdown, thermal stress, and electrostatic discharge—is essential for designing more reliable, high-performance semiconductor devices.
1. Metal failures: Electromigration, Stress Voiding
2. Oxide failures: Wearout, breakdown, HCI, NBTI
Engineering Challenges: Deep-submicron CMOS ICs need robust reliability models. Understanding these failure mechanisms is critical for chip longevity.
Interconnect Metals & Crystal Structure :
Metal Grains & Grain Boundaries : Interconnect metals are made of small, single crystals called grains. Grain surfaces are irregular and influence metal resistance. Grain boundaries (1–2 atoms wide) act as pathways for atomic movement. Fewer grain boundaries means stronger metal, as atoms have fewer paths to dislocate.
Metal Defects & Their Effects :
1. Types of defects:
(a) Interstitial defects : Small atoms like B & H fit between larger metal atoms.
(b) Substitutional defects : Atoms like Copper (Cu) replace Aluminum (Al) for strength.
(c) Vacancies : Missing atoms due to thermal vibrations, increasing with temperature.
2. Line & Area Defects:
Edge dislocations introduce stress points. Grain boundaries influence atomic motion and metal stability.
Metal Atom Motion & Failure Mechanisms :
1. Driving Forces for Atom Migration: Concentration gradient (Diffusion) , Temperature gradient (Thermotransport) , Voltage gradient (Electromigration) , Stress gradient (Stress voiding)
2. Electromigration & Stress Voiding: Major causes of metal failure in ICs.
Impact of Temperature on Metal Reliability :
Diffusion rate (D) increases exponentially with temperature. Modern ICs operate above 100°C, increasing metal atom mobility and potential failures. Understanding metal grain structures, atomic motion, and thermal effects is crucial for improving IC reliability and preventing failures due to electromigration and stress voiding.
Electromigration & Metal Reliability :
Electromigration (EM) is movement of metal atoms due to electron flow & temperature. Failure occurs when high current density & temperature cause, voids/material loss or extrusions/material accumulation.
Historical impact: Almost halted IC development in the 1960s until controlled methods were found.
Electron momentum transfer nudges thermally active metal atoms out of position. Aluminum (Al) atoms move in the direction of electron flow if a vacancy is available. Stress regions are formed i.e. tensile stress is formed where atoms leave or voids and compressive stress is formed where atoms accumulate I.e in place of extrusion.
Factors Affecting Electromigration :
(1) Atomic flux i.e. the rate of metal atom displacement.
(2) Current density. Higher current increases electromigration risk.
(3) Temperature. Higher temperature boosts atomic movement.
(4) Material properties. Al vs. Cu have different EM behaviors.
(5) Stress gradients. Areas of high tension/compression drive atomic motion.
Preventing Electromigration Failures: Copper (Cu) is more EM-resistant than Aluminum (Al), Use of wider metal lines to reduce current density. Addition of barrier layers to slow atomic movement. Optimizing temperature control in IC packaging. Electromigration is a critical reliability challenge in IC design, but proper material selection and design strategies help mitigate failures and extend device lifespan.
Metal Stress Voiding :
Discovered in the early 1980s. Differences in the thermal coefficient of expansion (TCE) between metal and surrounding passivation materials.
Three Key Conditions for Stress Voiding:
1. High Stress in the Metal : Caused by thermal expansion mismatches between metal and passivation which leads to mechanical strain in the metal structure. During fabrication, metal expands at high temperatures (~400°C) and bonds to passivation. When cooled to room temperature, metal contracts while passivation remains stable, creating high tensile stress.
2. Presence of a Defect: Small imperfections or void nuclei provide a starting point for stress concentration.The stress gradient formed encourages atomic movement.
3. Diffusion Path & Sufficient Temperature: Metal atoms need a way to move—grain boundaries typically act as diffusion paths. Elevated temperature enables atomic migration, allowing the void to grow.
When all three above conditions are met, stress voiding can lead to open circuits and device failure over time. Failure timing varies, could happen during fabrication, if metal quality is poor . If stress accumulates over time, can happen weeks or years later.
Ways to reduce stress voiding:
- Optimizing metal deposition techniques,
- Using stress-buffering layers,
- Control temperature variations during processing.
Stress voiding is a major reliability issue in ICs, caused by thermal expansion mismatches. Proper material selection and stress management techniques are essential to minimize failures.
Copper Interconnect Reliability :
Cu replaced Al in high-performance ICs due to its lower resistivity and higher melting point. This results in faster circuits with reduced RC time constants. However, Cu interconnects introduced new reliability challenges.
Electromigration in Copper : Still occurs despite stronger bonds, with activation energy (~0.8 eV) similar to Al. Unlike Al, Cu electromigrates at the Cu–passivation interface due to its weaker adhesion to the passivation layer. Higher granularity in Cu increases migration at grain boundaries.
Solution: Improvements in Cu processing techniques have increased activation energy, improving reliability.
High Diffusivity in Si & SiO₂ : Cu easily diffuses into silicon and oxide, contaminating ICs and degrading pn junctions. Barrier metals are used to contain Cu, preventing leakage. Tungsten (W) is used in the first metal layer to further separate Cu from transistor junctions.
Electromigration Failures in Vias : Cu vias require barrier liners, but failures often occur where the liner intersects Cu. Flux divergence at the bottom of vias creates voiding issues. 20% via voiding can lead to excess heat and cause the liner to fail thermally.
Stress-Induced Voiding (SIV) in Cu : Stress voiding can weaken Cu interconnects, making them vulnerable to EM failures. Wide metal leads feeding vias experience more stress voiding than narrow leads.
Solution: Strict design rules mitigate SIV by optimizing via location, metal width, and layout design.
Dual-Damascene Process Complexity : Unlike Al, Cu is not sputtered but deposited via a dual-damascene process. The quality of the Cu seed layer affects grain structure, influencing EM resistance.
Reliability of Cu with Low-k Dielectrics : SiLK™ (a polymer based low-k dielectric) reduces capacitance but worsens Cu electromigration reliability. Cu–SiLK™ t₅₀ values (time to 50% failure) were 3–5× lower than Cu–oxide interfaces.
Solution : Using barrier metals, optimized via layouts, improved Cu processing help mitigate Cu electromigration and stress voiding issues.
Oxide Structure & Defects :
Importance of Gate Oxides: Gate oxides, typically made of SiO₂ (silicon dioxide), are crucial for controlling channel charge in MOS transistors. Quality and thickness of these oxides are vital to transistor performance.
Historical Context: In the 1970s, oxide thickness was around 750 Å; today, it’s under 20 Å.Gate oxide electric fields in the early 2000s exceeded burn-in field strengths from the 1990s.
Challenges with Oxide Quality: Poor oxide quality leads to longer time to market and customer dissatisfaction.
Key Oxide Failure Mechanisms:
1. Wearout, 2. Hot Carrier Injection (HCI), 3.Negative Bias Temperature Instability (NBTI) (specific to pMOS transistors)
Understanding Oxide Structure: Imperfections at the Si-SiO₂ interface lead to unfilled bonds, creating sites for charge exchange. SiO₂ consists of Si atoms bonded to O atoms in tetrahedral structures. Bond angles vary (120° to 180°), weakening as they deviate from the mean (150°), contributing to oxide wearout.
Defects and Traps:
1. Traps : Defects in the oxide where charge can accumulate,impacting transistor performance.
2. Interface Traps: Located at the Si-SiO₂ interface, these traps can quickly exchange charge with channel carriers.
3. Border and Fixed Traps: Border traps are between 25 - 50 Å deep. Fixed traps are deeper than 50 Å and do not exchange charge, less relevant for modern failure mechanisms.
4. Impact on Performance: Charge exchange with oxide traps negatively affects transistor speed and reliability.
Gate Oxide Reliability in MOS :
Oxide Wearout : Good oxides can wear out and rupture when continuously subjected to charge injection. This failure is not related to fabrication defects; it’s a different mechanism that remains poorly understood despite extensive research.
Charge Injection and Failure: Every time a voltage is applied to a logic circuit’s gate oxide, a small amount of charge is injected into the oxide.
Impact on Product Lifetime: Oxide wearout time must exceed the expected lifetime of the product to avoid failure during usage. Miscalculations in wearout time can lead to severe consequences if premature oxide failure occurs.
Effect of Oxide Stress: Oxide wearout time decreases as stress on the oxide increases. Thin oxides, with their higher voltages and electric fields, are especially susceptible to premature wearout.
Oxide Field Strength: The oxide field strength is the force driving electrons across the oxide. As transistors continue to shrink (e.g., deep-submicron), oxide field strength increases, accelerating wearout.
Technological Trends: Since the late 1980s, as technologies have advanced, oxide field strength has progressively risen, intensifying the wearout risk for modern deep-submicron transistors.
Electron Tunneling in Thin Oxides: Significant tunneling occurs when oxide thickness is less than 40 Å, with tunneling current becoming worse as oxide thickness decreases to 20 Å or 15 Å. Increased gate currents from tunneling are key concerns for reliability and power in modern ICs.
Early Research and Breakdown: Early studies on transistor gate oxide shorts showed that gate capacitance could store enough energy to cause damage when a breakdown occurs. This energy release melts the silicon at the oxide interface, causing physical bonding of the polysilicon gate to the silicon substrate, leading to parasitic diodes or resistors.
Technology Scaling: As transistor technologies scaled, supply voltages dropped from 5-10 V to 1.0-1.2 V, and gate dimensions shrank from 1–5 µm to 90–130 nm.Gate capacitance decreased significantly, reducing the stored energy that caused violent thermal ruptures, shifting to more gradual breakdowns.
Oxide Wearout and Breakdown Models: Older thick oxides (>40 Å) have a different breakdown model than current ultrathin oxides (<30 Å). Breakdown in Ultrathin Oxides results in "soft breakdown," which increases noise in gate voltage or but does not cause immediate catastrophic failures.
Soft vs. Hard Breakdown:
1. Soft Breakdown (SBD): Occurs at low voltages and results in permanent gate current increase and noise. It is thought to be caused by trap-assisted conduction.
2. Hard Breakdown (HBD): Seen in older, thicker oxides. It causes severe gate voltage or current changes due to thermal events that merge materials above and below the oxide.
Ultrathin Oxide Breakdown :
Ultrathin Oxide Breakdown Stages:
1. Wearout: Gradual defect generation in the oxide until a conductive path is formed (percolation model).
2. Soft Breakdown: Leads to a permanent increase in gate current and noise at low voltages.
3. Hard Breakdown: Results in a continuous exponential increase in gate current.
Breakdown and Gate Voltage:
Breakdown time is related to gate voltage and oxide thickness. Electrons tunnel through the oxide, gaining energy and causing bond breakage when they strike the anode, which can release hydrogen ions (AHR) or create holes (AHI) that damage the oxide.
Percolation Model: The wearout and breakdown process involves the accumulation of damage sites (traps) in the oxide. When enough traps are aligned in a path, a thermally damaging current can flow through the oxide.
Transistor Behavior with Ultrathin Oxides:
Transistor Impact: Soft breakdown in ultrathin oxides has negligible impact on transistor performance, including gate voltage and transconductance.
Hard Breakdown: More severe and observed in nMOSFETs, especially in the gate-to-drain region. Soft breakdowns occur in the gate-to-source and gate-to-channel regions, with minimal effect on pMOSFETs.
Reliability Concerns:
Inverters: Oxide breakdowns weaken logic voltages, compromising noise margins and potentially causing functional failures in circuits.
Gate Stress: Greater stress on nMOS transistors occurs when the gate voltage is 0V, and drain voltage is V_dd, indicating a need for careful management of stress conditions. This breakdown and wearout model for ultrathin oxides highlights the shift from violent breakdowns in older technologies to more subtle, gradual failures in modern transistors, with implications for reliability in IC design.
Key Challenge: Data for high oxide field stress (>8 MV/cm) overlap for both models Long-term wearout studies take months/years Lower field & high-temp tests favored E-model for user conditions.
Key Oxide Failure Mechanism :
1. Hot Carrier Injection (HCI)
2. Defect-Induced Oxide Breakdown
3. Process-Induced Oxide Damage
4. Negative Bias Temperature Instability (NBTI)
Oxide Failure Mechanism :
Hot Carrier Injection: High drain-to-channel field accelerates carriers, causing , (1)Impact ionization → Electron-hole pairs scatter , (2) Some carriers enter the oxide, leading to trap formation . Affects transistor parameters.
Key Factors Influencing HCI: Higher supply voltage than design specs, Short channel lengths, Poor oxide interface or drain–substrate junctions etc. HCI is a gradual degradation, not catastrophic failure. HCI occurs during logic transitions, not in steady states.
What does technology sovereignty really mean in a world where chips power everything? 💡 In this electrifying episode of The Semiconductor Podcast (TSP), we dive deep with John, founder of TechSovereign Partners, to explore the hidden truths, strategic blind spots, and untapped potential of the global semiconductor ecosystem 🌍🔍.
🎯 What’s in the episode?
🚀 John’s dynamic journey from industry insider to thought leader and founder
🧠 What vendor lock-in, tribal knowledge, and scientific identity drag really cost your fab
🏭 Why mature-node fabs might be your strongest weapon—and why the world keeps ignoring them
🌐 How countries like India can realistically build chip sovereignty
🧰 Practical frameworks for fabs to balance innovation and execution
🔁 The quiet crisis of talent loss and knowledge transfer in fabs—and how to fix it
🔓 A rethinking of IP, collaboration, and non-unique solutions in semiconductor ops
🏆 Real-world engagements where execution trumped theory—delivered by a globally seasoned team
🔥 Whether you're a fab engineer, policymaker, startup founder, or simply a semiconductor enthusiast, this episode is packed with insight bombs and actionable takeaways. You’ll leave with a new lens on how fabs work, why some fail, and what it takes to build resilient, sovereign, and scalable chip ecosystems.
👷♂️ Engineers, don’t miss this—this is the conversation behind the conversations.
📺 Watch now. Think deeper. Build smarter.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape.
Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : John Ghekiere
John Ghekiere is the principal and founder of TechSovereign Partners, a consulting firm that helps semiconductor manufacturers and equipment OEMs solve tough problems fast. Drawing on a network of deeply experienced technologists across key fab disciplines, the firm works with manufacturers worldwide to stabilize performance, resolve yield issues, and guide critical decisions around tool strategy and manufacturing readiness. Before founding TechSovereign, John held senior technical and executive roles at Semitool, Applied Materials, and ClassOne Technology.
Credits :
Image by Lucas Wendt from Pixabay
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Today, The Semiconductor Podcast (TSP) marks a milestone—25 guests from deep tech conversations, ecosystem insights, and stories that matter.
To every guest who joined us, shared their time, vision, and expertise—thank you. You've shaped this platform into a credible voice for the semiconductor and deep tech community.
To our listeners and viewers, your encouragement, feedback, and quiet support fuel our mission. Whether you’ve tuned in for one episode or twenty-five, you're part of this journey.
TSP was born from a simple idea: to spotlight innovators, technologists, and leaders shaping the future of semiconductors in India and beyond. We’re just getting started.
With gratitude and excitement, Let’s keep building the ecosystem—one conversation at a time.
In this episode of The Semiconductor Podcast (TSP), we dive deep into one of the most exciting frontiers in semiconductor innovation—memristors. Our distinguished guest Dr. Debashis Panda walks us through his professional journey, from early explorations in device fabrication and nanoscale characterization to cutting-edge research in neuromorphic computing and healthcare diagnostics.
We unpack:
🔋 What exactly are memristors, and why they’re poised to redefine non-volatile memory.
⚡ How memristors compare to traditional memory in power efficiency, scalability, and AI readiness.
🧠 The potential of memristors in overcoming the von Neumann bottleneck, powering edge AI, and mimicking brain-like synapses.
💉 Applications in healthcare, from real-time glucose monitoring to cancer diagnostics and treatment of neurological disorders.
👚 The role of transparent neuromorphic devices in wearables and next-gen medical tech.
🛠️ Insights into fabrication techniques, key materials like ZnO, and tools like AFM, and electron-beam lithography.
🌐 How interdisciplinary knowledge—spanning electronics, materials science, and biology—is driving innovation across computing, AI, and medical devices.
We also explore the evolving career landscape in semiconductors:
🇮🇳 Opportunities in India’s growing ecosystem post–India Semiconductor Mission.
📚 Skill sets in demand for roles in memory devices, neuromorphic systems, and quantum-edge convergence.
🚀 How young researchers and professionals can future-proof their careers in this fast-paced field.
Whether you’re a student, technologist, policymaker, or curious mind, this episode offers a window into the next decade of semiconductor-driven transformation.
🔗 Tune in to explore how memory, AI, and biology are converging to build the future of intelligent machines and healthcare. 🌟
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Dr. Debashis Panda
Dr. Debashis Panda received his Ph.D. from IIT Kharagpur, followed by post-doctoral research experiences at NCTU Taiwan, the University of Utah (USA), and the National University of Singapore (NUS). He is currently serving as a Professor at the University of Techno India Group.
Dr. Panda was awarded the prestigious Indian Academy of Sciences Summer Research Fellowship in 2016 and the INSA Visiting Scientist Fellowship in 2017. He has also served as a visiting scientist at NYCU Taiwan (2022), NCTU Taiwan (2019), NPL New Delhi (2016), and IIT Kharagpur (2017).
His current research interests include the design and fabrication of low-power, highly reliable, transparent, and flexible wearable artificial inorganic/organic synaptic memristors for neuromorphic computing. He is a Fellow of the Semiconductor Society of India, Indian Physical Society, and Materials Research Society of India.
Notably, Prof. Panda completed a DST-SERB project in December 2021. An ANRF-CRG project is currently ongoing since February 2024. Under his principal investigation, a DST iTBI project was also granted. Recently, a DAE-BRNS project has been approved with Dr. Panda as the Principal Investigator. Additionally, he received AICTE-STTP funding in August 2020 and coordinated an ATAL-funded FDP in January 2024.
Dr. Panda has published over 52 international peer-reviewed papers in SCI/Scopus-indexed journals, 70 international conference proceedings, one textbook, and three book chapters with reputed international publishers. His work has received more than 2,500 citations.
He is a reviewer for several prestigious journals, including those from Springer Nature, IEEE, AIP, RSC, IOP, ACS, and Elsevier. He also serves as an expert reviewer for SERB project grants, the International European Research Council, and Chile Government research project grants.
Dr. Panda maintains active research collaborations with NYCU Taiwan, NTHU Taiwan, Dongguk University (South Korea), the University of Porto (Portugal), and several IITs and NITs across India.
Watch the podcast here :
