FEOL, MEOL, BEOL

In this article we will discuss about FEOL, MEOL, and BEOL. 

We will do a small recap of semiconductor fabrication process. 

Basic Process Steps in CMOS Fabrication:

                                        Fig. 1

The fabrication process of VLSI Integrated Circuits (IC) consists of a set of basic steps  starting from crystal growth, wafer preparation, epitaxy, dielectric and poly Si film deposition, oxidation, lithography, and dry etching.  Different patterns are developed using photo resist and mask and after forming the pattern photo resist is stripped out of the wafer. During the fabrication process, the devices are created on the chip and many of these basic steps are repeated multiple times. Depending on dose or energy of ion implantation process threshold voltage changes. Moreover position of the chip in the wafer determines the Threshold voltage and mobility. So all the chips fabricated on same wafer may differ in performance. Exactly identical performance is near impossible. 

End of Line (EOL):

Now lets discuss about End of Lines. 

The whole CMOS fabrication process is divided (see Fig2) into :

i.   FEOL or Front End of Line

ii.  MEOL or Mid End of Line

iii. BEOL  or Back End of Line

Fig. 2

In Front  End of Line we develop Transistor Level Layout Design on the wafer. The individual components like transistors, capacitors, resistors, etc.  are fabricated in the semiconductor. FEOL Consist of Chemical Mechanical Polishing a.k.a Polarization and Cleaning of The Wafer. Shallow Trench Isolation (STI) or LOCOS (tech node > 0.25 μm) Comes Under FEOL. FEOL  also Include Well Formation , Gate Module Formation, Source and Drain Module Formation.

In Middle End of Line or MEOL we do the Transistor Level Interconnect. MEOL consist of semiconductor wafer processing steps that create local electrical connections among source/drain/gate of transistors. Most important part of MEOL is Gate Contact Formation. It occurs after Front-End-Of-Line (i.e transistors/design-capacitor/design-resistor formation) Process Are Complete. Before Back-End-Of-Line metal/via/isolation-dielectric formation processes.

In Back End of Line we do the PnR level Interconnect through metalization/vias including Dielectric Separators among Various Metal layers.

                                              Fig 3

The above fig is showing the cross section of a chip and which layer is included in which EOL.

That will help you to relate the EOLs and layers.

Basic CMOS Structure and EOLs:

Lets see how a PMOS and NMOS are fabricated and connected to built the CMOS :

                        

                                             Fig 4.a

                                         Fig 4.b

                                             Fig 4.c

For PMOS there is N-well and P -select whereas for NMOS there is N-select. Inside N and P select  diffusion layers and Source and Drain contacts are created as shown in Fig 4a. Before creating contacts all the steps involved are in FEOL. After that Poly gates are created and connected with each other see Fig 4b. At final steps  Vdd, GND and Vout connections are created see Fig 4c. Connection between transistors , Source or  Drain contact creation and Poly gate creation and connection all are included in MEOL. Any step  beyond output contact creation is included in BEOL.

EOLs in Analog Layout Design :

  Fig 5 

Fig 5 shows steps involved in back end of IP design. These are the steps where hand made layout is created using commercial tool like Virtuoso. The steps goes in way like Schematic-Design, Layout, DRC/LVS, RC-Extraction, Physical Verification,  Characterization and Delivery

EOLs in SOC Design :

                                               Fig  6 

The Video Lecture On This Article Can be Seen Here :