For last few decades VLSI industry has kept pace with Moore’s law and transition from one node to another happened. As the node proceeds designers were able to produce faster, more powerful, more energy-efficient microchips.This constant advancement has fueled advances in everything from cloud computing to smartphones, virtual reality to robotics, and additive fabrication to the Internet of Things (IoT). But as the cost and complexity of each new process node has continued rising, advances have slowed noticeably, despite the fact that there are applications such as AI and machine learning, big data analysis and data center servers that require the latest and most powerful CMOS solutions.
FET was introduced in 1959 and from then FET has been mostly built in the plane of the silicon. In 2012, at 20nm, the industry made the first transition from “planar” MOSFETs to fin field-effect transistor (FinFET) architectures to maintain the Moore’s Law scaling path. In a FinFET, the channel between source and drain terminals is in the form of a fin and the fin is contacted on three sides by the gate. This structure provided better control of the channel formed within the fin. As a result, FinFETs helped significantly with current leakage. Since then, fin height has been increased to obtain a higher device drive current at the same footprint. Today's designs place the gate stack directly above the channel area. One problem is that as these structures become smaller, it becomes more difficult to block the charge leak across the transistor. With FinFETs, the gate surrounds the rectangular silicon fin on three sides, leaving the bottom side connected to the body of the silicon. This allows some leakage current to flow when the transistor is off. The resulting leakage leads to hotter, less power-efficient microchips. As scaling is pushed beyond 5nm, the FinFET road-map seems to be coming to an end . The initial technology beyond the FinFET will be the stacked Nano Sheet transistor. This is broadly part of a concept that may also be described as gate all around or GAA transistors, which address several challenges around FinFETs for the 3nm node and beyond, promising performance boosts of more than 25 percent and power consumption reductions of more than 50 percent. Instead of using a stack of Nano Wires to bridge the source and drain, a stack of thin sheets of silicon is utilized. Unlike FinFET technology, in Nano Sheet technology the gate surrounds the channel region in its entirety, providing even better control of current leakage. This stacked structure supports far more advanced semiconductor fabrication processes, including a channel region that is tilted upward to create a wider path for current. In Nano Sheet FET the channel region consists of multiple, horizontal, nanometer-thin sheets stacked atop one another. A gate fully wraps around the channel to provide better channel control compared to a multi-gate FinFET with limited additional process complexity.
One of the key advantages of a Nano Sheet device is its short channel control, which is critical to threshold voltage variation (Vth). Smaller Vth variation is crucial for good device. Nano sheets offer excellent electrostatics and short channel control, and can be fabricated with minimal deviation from FinFET. On the other hand, multiple Vth here comes with more restrictive requirements on dimensions (because of limited-sheet-to-sheet space). Still, researchers have demonstrated nanosheet transistors with more than 50 percent lower Vth variations.
Key advantages of Nano Sheet FET over FinFETs includes design flexibility like adjusting the effective width of the transistor channel. More width means you can drive more current and switch a transistor on and off more quickly. These sheets can be made wide to boost current, or narrow to limit power consumption. For example, a Nano Sheet with a wider sheet provides more drive current and performance. A narrow Nano Sheet has less drive current, but takes up a smaller area.
Not all chips currently being produced require FinFETs. Analog, RF and other components are built around more mature processes and are still in high demand. FinFETs will still be viable for chips from 16nm to 5nm, while planar transistors will remain the mainstream technology at 22nm and above.
Fig. 3: Technology nodes over the past and prospective vision for future
The adoption of nano-sheet FET should follow the adoption of FinFET with a 10-years shift. Is it anticipated that the 3-nm node will announce the start of a migration from FinFET to NsFET, to enable further gains in current drive while reducing the device surface, thus enabling smaller, faster and more energy-efficient chips (Figure 3). The three different categories of applications should remain: high performance computing (severs, data centers), general purpose (laptops, gaming), and low power (mobile, IoT) with significant differences in terms of acceptable leakage current (IOFF).Moving to Nano Sheet FETs varies depending on the foundries. This situation is somehow similar to the transition from MOSFET to FinFET initiated by Intel in 2011. Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s FinFET transistors to GAA FETs at the 3nm and 2nm nodes, starting either next year or in 2023. GAA FETs hold the promise of better performance, lower power and lower leakage. Samsung plans to introduce the world’s first nanosheets at 3nm in the 2022-2023 time frame. TSMC is developing 2nm GAA for initial launch in 2024 or 2025.The technology will require entirely new fabs. With the cost of these new fabs in the $20 billion range, this isn't something the industry is approaching without careful consideration.
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