In this article we will discuss about process corners. Process corners are results of variations occurring in the attributes of transistors (i.e. length, widths, oxide thickness) during semiconductor fabrication processes. Since process corners are termed with NMOS and PMOS lets start our journey with basic CMOS layout and their connection and then a small recap of VLSI fabrication process.
Basic CMOS Structure:
Lets see how a PMOS and NMOS are fabricated and connected to built the CMOS :
Fig 1.a
Fig 1.c
For PMOS there is N-well and P -select whereas for NMOS there is N-select. Inside N and P select diffusion layers and Source and Drain contacts are created as shown in Fig 1a. After that Poly gates are created and connected with each other see Fig 1.b. At final steps Vdd, GND and Vout connections are created see Fig 1c.
Basic Process Steps in CMOS Fabrication:
Fig. 2
The fabrication process of VLSI Integrated Circuits (IC) consists of a set of basic steps starting from crystal growth, wafer preparation, epitaxy, dielectric and poly Si film deposition, oxidation, lithography, and dry etching. During the fabrication process, the devices are created on the chip and many of these basic steps are repeated multiple times. Depending on dose or energy of ion implantation process threshold voltage changes. Moreover position of the chip in the wafer determines the Threshold voltage and mobility. So all the chips fabricated on same wafer may differ in performance. Exactly identical performance is near impossible.
NMOS vs. PMOS :
Now lets see how a PMOS is different from NMOS with respect to performance.
Mobility of electron is twice that of the hole Mobility and ON-Resistance of NMOS is half of PMOS.
Consequently, to balance out the same channel resistance and mobility, PMOS is made 2x in size of NMOS. A CMOS contains this balanced NMOS-PMOS pair. If we do not do the balancing , for the same dimensions PMOS is slower than NMOS by birth. However, PMOS circuits have some advantages over NMOS.PMOS technology is low cost process and highly controllable. It has good yield and high noise immunity. If not CMOS , NMOS based ICs can be smaller for the same complexity and silicon area as compared to its PMOS Counterpart.
Process Parameters :
Parameters of a semiconductor fabrication are generally statistically distributed [ mean, standard deviation etc]. The PVT stands for Process, Voltage, Temperature. These three parameters have direct impact on performance of cells and that is termed as corners. An IC should operate in wide variety of conditions and PVT corners are a reference to understand the optimum operable condition of the chip.
• Process related variations termed as P occurs due to variation in temperature, pressure, dopant concentration, wavelength of UV ray etc and results in variation of oxide thickness, dopant concentration, mobility, RC value and transistor dimension, Poly width, Metal Width etc.
• Variable operating conditions include : Operating-Voltage/Die-Voltage (V)
• Operating Temp (T) within range of -40 to 125 Degree Celcious (T).
Fig 3
FEOL :
The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual components like transistors, capacitors, resistors, etc. are fabricated in the semiconductor.
FEOL Consist of Chemical Mechanical Polishing a.k.a Polarization and Cleaning of The Wafer.
Shallow Trench Isolation (STI) or LOCOS (tech node > 0.25 μm) Comes Under FEOL.
FEOL Also Include Well Formation , Gate Module Formation, Source and Drain Module Formation.
MEOL:
MEOL consist of semiconductor wafer processing steps that create local electrical connections among source/drain/gate of transistors. Most important part of MEOL is Gate Contact Formation.
Most important part of MEOL is Gate Contact Formation.
It occurs after Front-End-Of-Line (i.e transistors/design-capacitor/design-resistor formation) Process Are Complete. Before Back-End-Of-Line metal/via/isolation-dielectric formation processes.
BEOL:
The Back-End-of-Line (BEOL) is the remaining portion of IC fabrication where the wiring is done through Metalization/Vias including Dielectric separators among various metal layers.
Through Metalization/Vias including dielectric separators among various metal layers.
BEOL goes like :
1. Silicidation of Poly-Silicon and Source/Drain Diffusion.
2. Then adding a Pre-Metal-Dielectric(PMD) & CMP processing it !
3. Make holes in PMD & create contact through It.
4. Add metal layer 1.
5. Then add dielectric layer a.k.a Inter-Metal Dielectric (IMD).
6. Through CVD make vias through IMD to connect lower metal layer with higher metal layer .
7. Carry on last three steps until all the metal layers as per the tech node are done.
8. Add final passivation layer to protect the chip.
Fig 4
The term corner refers to an imaginary four box that ensures specific performance of the circuits at each of its corners. Each corners i.e extreme limits specifies some sort of performance boundary condition for the design under consideration. Process corners represent the extremes of silicon fabrication process parameter variations for a fabricated circuit. Mixed name corners like fast-slow and slow-fast and are refereed to as skew corners. When the parameters of a transistor are set in such a way that the transistor operates fast then it is known as a fast corner. A single circuit will perform differently in each of the process corners. A single process corner may show slightly different performance for a given circuit from one wafer-lot to another wafer-lot. The testing of the circuit performance at each corner is termed as "characterization". This word is used frequently with Standard Cells. Two-letter designation (TT,FF,SS etc) points to N-Channel MOSFET (NMOS) corner and P-Channel (PMOS) corner for a CMOS structure respectively.
FEOL Corners :
Common FEOL corners are FF,SS,FS,SF,TT
BEOL corners :
C -Worst, C Best, Cc Worst, RC Best, Rc Worst
Basic Nomenclature :
• NMOS can be slow, typical, fast (S, T, F).
• PMOS can be slow, typical, fast (S, T, F).
• Temperature can be hot, typical, cold (S, T, F).
• Vdd can be high, typical, low (F, T, S).
Fig 5
Example :
Here are some example of Process corners and their detailed description.
Elaborate Process Corner Label may include NMOS, PMOS, Temp, Vdd.
• TTTT = typical NMOS, typical PMOS, room temp, nominal supply.
• SSSS = slow NMOS, slow PMOS, hot temp, low supply.
• FSSS = fast NMOS, slow PMOS, hot temp, low supply.
Similarly using basic nomenclature mapping we can construct elaborate nomenclature of process corners.
Variation of specific Figure of Merits (FOM) of any Design under Consideration are observed across all the permutation and combination of P, V and T. The permutation and combination get complex when BEOL(RC) corners are taken into consideration.
Real Corners :
Real corners combines both FEOL and BEOL parameters. A standard corner data sheet is shown below:
Watch the video here :
Courtesy : Image by www.pngegg.com
