Buried Power Rail

Belgium based IMEC  has announced functioning devices using a new technique of burying power rails below active devices. Is this technique effective in addressing power rail congestion issues prevalent in state-of-art devices. Buried power rail is usually referred as BPR. Its is a new topic and before diving deep into it, lets’s start with some definitions :

1. What is a power rail ?

Power rail can be defined as the voltage source within the device from which its various functions can draw power.

2. What is routing congestion in VLSI?

When the number of routing tracks available for routing in a given location is less than the number necessary, the area is considered congested and hence, is termed as congestion in VLSI Physical Design Flow. The number of nets that may be routed through a given region will be limited.

3. Now What is a buried power rail?

A buried power rail is a power rail found inside the semiconductor substrate instead of on a metal layer. The rail itself is constructed to run underneath the active layer where semiconductor components are found (i.e. transistors and diodes).

IMEC is Interuniversity Microelectronics Centre. Its an international research & development organization, active in the fields of Nano Electronics and digital technologies. Their headquarter is in Belgium. In 2019 IMEC first announced about BPR and continuously working on that. In 2021, IMEC for the first time showed backside connectivity through nTSVs landing on metal-1 pads in the wafer’s front side. In 2022 , IMEC has presented the first experimental demonstration of a routing scheme for logic ICs with backside power delivery enabled through nano-through-silicon-vias (nTSVs) landing on buried power rails (BPRs). The BPRs connect to scaled FinFET devices and their performance was not impacted by backside wafer processing. Since IMEC’s first announcement in 2019, different implementations have been proposed.

Designing semiconductor devices presents a whole range of different challenges including quantum tunneling, causing current leakage, overheating devices, propagation delay, and feature sizes. Once the active components of a semiconductor are designed (i.e. transistors), the remaining layers are used to route signals and power. This stage is very similar to routing a PCB, and as such can suffer from similar problems.

Generally, routing power rails is the last step in a design as routing signals takes priority (especially in high-frequency circuits), and as such is given the topmost layer (called M1). As a result, power rails can be far from their active components while the use of many interconnects introduces resistance, inductance, and reflections.

IMEC demonstrates FinFET CMOS with Buried Power Rails.The demonstration utilises FinFET CMOS to show that buried power rail (BPR) technology can work with modern technologies.A paper was published in 2019 by a group of researchers from ARM and IMEC on this topic. In this paper researchers showed that buried rails with front-side power delivery system could improve the worst-case IR drop from 70mV to 42mV (~1.7X reduction) whereas buried rails with back-side power delivery substantially reduce IR drop to 10mV (a 7X reduction).One of the concerns of using BPR technologies in semiconductor devices is the active layer's interference when embedding BPRs. Since the layer sits below the active layer, and these layers are created one after the other, there is a chance that device performance can worsen as a result of stress, degradation, and metal contamination. However, the demonstration by IMEC shows that these worries can be avoided to create fully-functional active devices down to the 3nm scale. The BPRs developed by IMEC are made from Tungsten (W), and via interconnects to this layer used Ruthenium (Ru). The effectiveness of the BPRs was further displayed after 900 hours of continual use at 330°C at a current of 4MA/cm2 with no electromigration failures being observed.

After discovering that the BRPs are made of tungsten, the question of resistance immediately comes to mind. Copper is a highly conductive element, and as such has a low resistance, but tungsten has a resistance almost four times higher than copper. As such, tungsten rails would have an additional power loss of 4 times that of copper, and therefore 4 times greater energy loss.

However, while tungsten may have a greater resistivity than copper, using BRPs provides advantages not possible with M1 power routing. Routing power rails below the active layer offers a shorter routing distance between active devices and power rails (remember that CMOS technology requires a direct connection to power rails VDD and VSS). As such, the total length of wire between the power and individual active devices is reduced.

The second advantage is that designers are given more freedom on routing layers by moving power routing below the active devices. As such, signal connections can be reduced in length which allows for greater speed of operation. A secondary study on BRPs has confirmed such advantages and has stated that grid power distribution can improve SRAM by 28.2%.

Buried Power Rails are still in development, and add an entirely new production step to a semiconductor. But their advantages are clear with reduced power rail length, improved efficiency, and a more compact design.

In the current technology scaling paradigm, semiconductor device physics and conductor parasitics are fundamentally limiting microprocessor performance beyond the 5nm process node. Many experiments showed promising returns from BPR and back-side power delivery. However, there are a number of designs, manufacturing technology, and packaging complexities need to be addressed and resolved before it is possible to fully enable back-side power delivery with BPRs for wide-spread industry adoption.

Video on this topic is here : 

Courtesy : Photo by Laura Ockel on Unsplash