1. What Is Latch Up Phenomenon?
A latch-up is a destructive short circuit phenomenon to the CMOS Structure. It can be defined as a low resistance path between voltage levels. It is caused by low-impedance path between the power supply rails of a MOSFET circuit through a PNPN parasitic structure underneath. The circuit function is disrupted by latchup and currents are frequently large enough to cause permanent damage.The parasitic PNPN structure resembles and equivalent to Silicon Controlled Rectifier (SCR) structure.
A PNPN structure which created by a PNP and an NPN transistor stacked next to each other. Immediately after latch up trigger, one of the transistors starts conducting and the other one begins follows it by start conducting.They both stay in saturation for as long as the structure is forward-biased and some current flows through it.
Fig 1 : SCR and I-V characteristics
Revisit SCR PNPN Structure:
An SCR (silicon controlled rectifier), a four-layer pnpn device formed by at least one pnp and at least one npn transistor connected as shown in figure. By default an SCR is a normally in switch-off state i.e. "blocking state" with negligible current flowing through it.Hence the SCR presents a high impedance path between supplies. And its behavior changes to similar to that of a Forward-Biased diode rectifier[conduction from anode(A) to cathode(K)] on application of a control signal is applied to the gate(G). When triggered into its "conducting-state" the SCR is said to be "latched" to the conduction.
Lets understand the how the SCR works and latchup happens from the BJT equivalent circuit. Current from the gate injected into the base of Q2. This causes current flow in the base-emitter junction of Q1. Q1 fortifies further current to be injected into base of Q2. This positive-feedback condition ensures that both transistors saturate. Consequently, the current flowing through each transistor ensures that the other remains in saturation.
When Does The Latch-Up Starts ?
The latch event get triggered by a positive or negative voltage surge on any input/output pin of a CMOS chip that exceeds the rail voltage by more than a P-N Junction drop. Alternatively, if the supply voltage exceeds its MAX-Rating, trigger may come from the respective transient spike.Nearby junctions that are forward biased could inject minority carriers into the region. If the difference between Vdd and Vss is large enough, due to constant voltage stress over time , avalanche breakdown of the well-substrate junction occurs. For Space-Application-Chip, trigger may come from ionizing radiation induced photo-currents or from microwave interference. Another trigger may come from an electrostatic discharge (ESD) event. All of the trigger finally leads to a breakdown of an internal junction of the CMOS.
Parasitic PNPN Structure Inside CMOS:
Take a close look at the below diagram. Parasitic R and C are included in the CMOS structure.
Both parasitic BJTs biased into the forward active region. The emitter(E)-base(B) junctions are forward biased. Consequently implies minority carrier injection occurs.The beta gain product must be sufficient to allow regeneration. The power supply must be capable of contributing current and voltage greater than the current and voltage of the holding point.
Latch-up Mitigation : Fabrication Process
During the semiconductor process, insulating oxide is put into a trench that surrounds both the NMOS and the PMOS transistors. Hence this process step is called Shallow Trench Isolation (STI). The STI breaks down the formation of the back to back parasitic PNPN structure between these transistors. FDSOI or UTSOI Technology based silicon-on- insulator devices are inherently latch-up-resistant.
Latch-up Mitigation : Physical Design
1. Topology based Check during IP/Block-Level Design : Through various EDA tools preventive latch-up detection is done during early during the schematic design.
2. Hot-Junction Detection & Modification : Connection of MOS devices with direct , i.e low impedance, connections to I/O ports called “hot”connection because it allows a current injection into parasitic PNPN structure to trigger latch-up. A series resistor is inserted between IO-Pad and MOS device to reduce current and hence stop the latch-up .
3. Guard Ring Protection : Guard Rings are implemented around both NMOS & PMOS to collects parasitic currents from PNPN structure.
4. DRC Enabled Preventive Check : Foundries Typically Provide DRC Spacing guidelines through DRM to avoid latch-up failures.
No Chip can tolerate latch-up. Latch-up will cause burn out. The best practice is to be aware of its possibility, understand it and take preventive measures. Channel protectors (i.e STI) may provide a simpler, more-compact, and more generally stable solution, resulting in a robust system likely to give fewer problems in the field. Several Physical Design Methods are there to make the chip latch-up-proof
