In this article we will discuss about Multi Bit Flip Flop (MBFF), how MBFFs are created by combining single bit FFs and how MBFFs are integrated into the VLSI design flow.
MBFF and Its Significance in Chip Design :
MBFF is one of the most effective methodologies in saving both chip area and power consumption. Advanced clock tree synthesis flow are used to implement MBFF. After usage of MBFF , total length of clock tree is effectively minimized. Consequently this leads to reduction of clock tree buffers and hence total clock tree power. Reduction of Clock tree buffers also improves overall design skew and latency.Reduction of Clock tree and scan nets helps in improving the routing congestion. Area of multi-bit flip flops is less than equivalent number of single flip flops because transistor level escalation of cell layout, which includes shared logic and power supply.
Single Bit Flip Flop :
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Fig. 1 : Single Bit Master Slave (MS) Flip Flop
2-Bit-MBFF :
Two 1-bit FFs grouped into 2-bit MBFF, called also 2-bit FF.The figure shows the block diagrams of 1- and 2-bit flip-flops. If we replace the two 1-bit flip-flops by the 2-bit flip-flop the total power consumption gets reduced because the internal 1-bit flip-flops can share the same clock Buffer inside MBFF. In a similar manner, grouping of FFs in 4-bit and 8-bit MBFFs are possible too. Actually using MBFFs we are reducing power consumption and overall area.
4-Bit-MBFF :
Here we can see how 4 single bit FFs are combined and a 4-Bit FF is formed. The optimization actually comes at transistor level while doing IP design and overall turn around time gets reduced.
Criterion of Implementation:
RTL-Synthesis and Physical Implementation(PD) tools can organize multiple register bits into groups called multi-bit components in the RTL bus inference flow or banks in the placement aware flow. This process is also known as vectoring. To perform mapping from single-bit to multi-bit registers, the tool checks for matching pin functions and naming conventions in the multi-bit register pins.The bare minimum requirement for such flow is that the logic Library(Front-End Library) and Physical Library(Back-End Library) should contain both single-bit and multi-bit library cells. The design of the multi-bit cells must meet certain criteria so that the EDA tool can recognize them as functionally functionally equivalent to a group of single-bit cells.
MBFF in Design Implementation:
RTL-Compiler(Synthesys) and PnR Tools(Physical Design) are used for implementation of MBFF. First We exclude the unnecessary cells from getting swapped with its corresponding multi-bit version.The cell types include RTL specified cells, scan cells, macros, enable registers,debug cells, and design specific cells. Set the maximum capacitance tolerance allowed for clustering the FF cells.The size of the merged cell should be controlled based on timing or power requirements. For timing requirement,the smallest cell with Cmax bigger than the original cell is taken. For power requirement, the smallest cell with largest Cmax smaller than the original cell is taken. The single-bit registers groups should be identified that can be replaced by multi-bit registers and then modify the netlist accordingly or generate a banking script file which can then be sourced back into the tool to replace single-bit cells with multi-bit cells. This is achieved using user defined input bit-mapping file. All the desired or intended single-bit cell groups in list are replaced by corresponding multi-bit cell as per mapping. If the multi-bit library cell has a larger bit-width than the total bit-width of the specified cells, the pins of the unused bits of the cell are left dangling. If a pin of a specified cell does not have a corresponding pin in the multi-bit library cell, the pin is left disconnected. For the final merging of cells, the multi-bit register is created, the single bit cells are disconnected from the nets and then those nets are re-connected to the multi-bit registers.
VLSI Design Flow:
Now lets see exactly where in the VLSI flow MBFF's are inserted. First take a look at the VLSI Design Flow.
MBFF in Front-End Design (FE) Flow:
Fig. 5: Inclusion of MBFFs in Front End Flow
In front end flow once we have RTL Design which we must add FE Cell Library with MBFFs and design constraints. Then we will go for flip flop grouping and replacing FFs with MBFFs i.e. logic optimization with MBFF. Once optimization is done we will include DFT and Scan chains and do our synthesis.
MBFF in Back-End Design (PD) Flow:
Fig. 5: Inclusion of MBFFs in Back End Flow
Now lets see how MBFFs are incorporate in back end flow. In back end we start with the design with MBFFs received from front end flow. Then we do placement followed by timing and placement related placement analysis. Next comes post placement MBFF clustering or grouping. In this step we incorporate back end or physical design library with MBFFs and density or timing constraints. Then legalization and clock tree synthesis is done. Then we complete routing and layout design.
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