In this article we will discuss about the significance of Physical Design. So lets start the journey by knowing what PD is all about.
1. What is Physical Design (PD) ?
PD is the Process-Steps of Transferring Digital/Analog Circuits into Silicon. This is the Back-End Part Of The Standard Design Steps. Actually whatever circuit we intend to fabricate on Silicon , we start with design spec. Then we translate that spec into RTL code and gradually with inclusion of timing data and other parametric value we create a mask which will actually transfer the design into CMOS on Silicon. Transferring of design from merely gate level data to actual physical silicon is done by back end steps which in total called Physical Design. Designing the chip in physical real world (from gate level data) is called physical design. PD Helps Circuit Components and Their Wiring To Be Realized into Physical Masks For Silicon Chip.
The Word Physical in Physical-Design came from the Physical aspect of the design methodology.
1. Spatial Embedding of Active and Passive Devices on Silicon-Wafer.
2. Usage of Wiring Interconnects(Metal/Via) and Separating Dielectrics. Separating Dielectric and gate dielectric both are not same. Gate Dielectric is at device level whereas the separating Dielectric is at wiring/interconnect level. This separating Dielectric keeps any two metal layer insulated from each other. Shorting is the last thing we desire while handling any two current carrying metal wire!
3. Induced Parasitic Resistance(R) , Capacitance(C) and Coupling Capacitance(Cc). These are the by products once the circuit is realised in Silicon.These are not the part of design capacitance or resistance. These are extras and come into play when the circuit is realised on Silicon. Since they are very much present and create unwanted interference in circuit performance physical design in advance include their presence and calculate the effect.
4. Evident Effects of Physical Phenomena Such as Delay, Noise, Power, Leakage, Reliability and Manufacturability are Considered in PD. In the front end part the circuit is a pure circuit and no data related to Delay, Noise, Power, Leakage, Reliability and Manufacturability is included there. We encounter all these physical phenomenon in physical domain and therefore we include them in back end.
5. Design related issues like Design-Rule-Error , Antenna Issue and Mask Issue due to Diffraction of EUV Light we consider during back end design. Design rules are provided by foundry as Design Rule Manual or DRM. Antenna rules are there to prevent from Antenna issue. Mask Issue due to Diffraction of EUV Light is basically engineering issue related to fabrication and that its effect is also included in back end.
2.Why Physical Design is Must ?
Doing Layout is very time consuming in both Analog and Digital Design. A Chip’s Switching Speed is critical in today’s scenario and signed-Off by Post-Layout Static-Timing-Analysis (STA). STA verifies the speed of operation and correctness of the chip's functionality in that speed of operation. Post-layout STA comes under PD. On-Chip electrical characteristics of logic gates depend on the aspect ratio of P-MOS/N-MOS. Electrical characteristics is basically I-V characteristics of MOSFET and we all know value of I is dependent on W and L variation of the MOSFET. That is true for both p and n MOSFET. Current and voltage level is further affected Induced Parasitic Resistance(R) , Capacitance(C) and Coupling Capacitance(Cc). Predictive detection and prevention of Reliability Issues Due To IR-Drop or Electromigration (EM) are Necessary. IR and EM are two important part of analysis in the entire back end. By doing these analysis we can prevent many issues and take preventive measures. Chip Lifetime is predicted by Aging Analysis. It helps Manufacturers to Quote Chip Guarantee/Warranty Period. It actually shows for how long the chip will be able to maintain its figure of merit. Layout Equivalence Check or LEC determine the intended functionality vs realized functionality on layout.
3. PD Steps in Analog and Digital Design (ASIC/SOC)
Lets discuss the physical design steps in analog and digital design in Analog design PD starts after Schematic-Design which is done in front end. Then comes layout. There are several variation in custom and semi-custom layout. Once the layout is done DRC and LVS check are done on that layout.If any error found in these steps we might need to go back to layout step. Once the DRC and LVS is clean we move forward and do the parasitic R and C extraction. Then we go towards physical verification steps like IR Drop analysis, Electro Migration analysis, Antenna checks etc. Once all the verification steps are done properly we will move to electrical and timing characterization and ready for the delivery. If it is a analog block then it will be delivered as a analog IP and if its a analog chip the GDSII file is delivered to the foundry.
Now lets discuss the physical design steps in digital design. After front end steps the synthesized netlist is moved to the pre-layout static timing analysis. Now we enter back end.First we do Floor Planning and PnR i.e Place and Route. Floor planning is keeping different blocks at different place and do the area budgeting. Then we do placement of these blocks and do the metal routing and connectivity. Then we do DRC and LVS check on the layout that has come out of the Floor-Plan and Routing stage. Then we do the parasitic RC extraction. Then we proceed towards the STA and Physical Verification. This STA is Post-Layout STA. In physical verification we do IR Drop analysis, EM analysis,Antenna Rule Check etc. Next comes Formal verification and sign off.
