In this article we will discuss about Design Rule Check and its importance in VLSI.
Design Rule and Design Rule Check :
Design Rule are set of rules which a designer must follow to create the layout in GDS/ GDSII format so that the design is eligible for manufactured in intended technology. All the rules comes from foundry and written in Design rule manual or DRM.
Design Rule Checking or DRC verifies whether an IC has been designed by following constraints imposed by the process technology to beused for its manufacturing. In short DRC is the process to confirm that design rules have been followed while designing the circuit. DRC checking is an important part of the physical design flow. It ensures that the design will not result in a chip failure.
Design Rules specify a minimum feature size or spacing requirements or some geometric constraints between layers/masks of the same type or between different types.Design Rules are mentioned in ASCII/PDF Format in the Design Rule Manual/Document. Each Physical Verification Tool have its own format of reading the Design Rule.It means design rule files for one tool cannot be used for a second tool. Second tool from another EDA vendor require different set of files. However, fundamentally the rules are same in both set of files. Design Rules Set are usually supplied by foundry and comes along with the PDK/DK distribution. Technically the Design Rules are the interface between design-engineer from SOC design house and Process Engineer from foundry. Rules are written in a way that they can be forward compatible to upcoming generations. Design Rules ensure that design made through EDA-Software will perform as expected and with proper functionality after fabrication.
The whole VLSI design flow is divided into front end and back end. Design rule check is done in back end part.
Back-End in Analog and SOC Design Flow:
Now let's see what are the various mask layers are used to create layout on the silicon wafer. Layout is nothing but layout of the mask on the wafer. Each part is created with single mask . Metal layers like Metal 1, Metal 2, Metal 3, Metal 4 and we can go upto layers permitted in that particular technology node. Then we can have different types of Well (n and p) and Poly (gate). Then we can have the contact as Cont layer and Via. Via is used to connect two metal layers in routing or BEOL stage and cont is used as source or drain contact.Cont is at FEOL layer. If you want to understand FEOL and BEOL in detail read our article on this topic. Then comes active
Fig 3(a)
Fig 3(c)
Lets see how a PMOS and NMOS are fabricated and connected to built the CMOS. From above three figures we can see MOS is fabricated in layer by layer using different masks. Its done in batch process i.e, when Metal 1 is fabricated , it is done across the whole chip. Similarly all the other layers are fabricated.
For PMOS there is N-well and P -select whereas for NMOS there is N-select. Inside N and P select diffusion layers and Source and Drain contacts are created as shown in Fig 3a. Before creating contacts all the steps involved are in FEOL. After that Poly gates are created and connected with each other see Fig 3b. At final steps Vdd, GND and Vout connections are created see Fig 3c. Connection between transistors , Source or Drain contact creation and Poly gate creation and connection all are included in MEOL. Any step beyond output contact creation is included in BEOL.
Sequence of Mask Layer :
Fig 4. Different Mask Layers
Above figure shows how the mask sequence is introduced in the CMOS fabrication process. It is a typical example we are using to discuss the topic. The above figure shows the sequence starting from N-well, Poly, N+ diffusion, P+ diffusion, Contacts and then Metl layers. So this way sequentially the layers are picked up from the layout and fabricated on the Silicon wafer.
Design Rules :
Each semiconductor process step imposes a set of design rules on the geometric component size, relative position, etc. These rules have subtle differences however the common theme remains the same, mainly to use the proper geometric shape and separation to create a reliable manufacturing process. Some Rules are :
Classification of Design Rules :
If we classify based on unit, design rules are Micron rules and Lambda rules. On the other hand if we classify based on spacing,there are Inter-layer rule and Intra-layer rule.Inter layer rules are for two different layers regarding spacing between them and all. Intra-layer rules are for same layer segment .
1. Micron Rules : Here, the layout constraints, such as minimum feature sizes and minimum allowable feature separations, are stated in terms of absolute dimensions in micrometers or nanometers.
2. Lambda Rules : Here, the layout constraints are expressed in terms of a single parameter λ. Hence allow linear and proportional scaling of all geometrical constraints.
So Micron rule is a absolute rule and lambda rule is a relative rule.
