Design Rule Check in VLSI

In this article we will discuss about Design Rule Check and its importance in VLSI.

Design Rule and Design Rule Check :

Design Rule are set of rules which a designer must follow to create the layout in GDS/ GDSII format so that the design is eligible for manufactured in intended technology. All the rules comes from foundry and written in Design rule manual or  DRM. 

Design Rule Checking or DRC verifies whether an IC has been designed by following constraints imposed by the process technology to beused for its manufacturing. In short DRC is the process to confirm that design rules have been followed while designing the circuit. DRC checking is an important part of the physical design flow. It ensures that the design will not result in a chip failure. 

Design Rules specify a minimum feature size or spacing requirements or some geometric constraints between layers/masks of the same type or between different types.Design Rules are mentioned in ASCII/PDF Format in the Design Rule Manual/Document. Each Physical Verification Tool have its own format of reading the Design Rule.It means design rule files for one tool cannot be used for a second tool. Second tool from another EDA vendor require different set of files. However, fundamentally the rules are same in both set of files. Design Rules Set are usually supplied by foundry and comes along with the PDK/DK distribution. Technically the  Design Rules are the interface between design-engineer from SOC design house and Process Engineer from foundry. Rules are written in a way that they can be forward compatible to upcoming generations. Design Rules ensure that design made through EDA-Software will perform as expected and with proper functionality after fabrication. 

The whole VLSI design flow is divided into front end and back end. Design rule check is done in back end part. 

Back-End in Analog and SOC Design Flow:

Lets discuss the steps involved in analog and digital design. 

In Analog design PD starts after Schematic-Design which is done in front end. Then comes layout. There are several variation in custom and semi-custom layout. Once the layout is done DRC and LVS check are done on that layout.If any error found in these steps we might need to go back to layout step. Once the DRC and LVS is clean we move forward and do the parasitic R and C extraction. Then we go towards physical verification steps like IR Drop analysis, Electro Migration analysis, Antenna checks etc. Once all the verification steps are done properly we will move to electrical and timing characterization and ready for the delivery. If it is a analog block then it will be delivered as a analog IP and if its a analog chip the GDSII file is delivered to the foundry. 

                  Fig 1. Analog and ASIC/SOC Design Flow

Now lets discuss the digital design steps. After front end steps the synthesized netlist is moved to the pre-layout static timing analysis. Now we enter back end.First we do Floor Planning and PnR i.e Place and Route. Floor planning is keeping different blocks at different place and do the area budgeting. Then we do placement of these blocks and do the metal routing and connectivity. Then we do DRC and LVS check on the layout that has come out of the Floor-Plan and Routing stage. Then we do the parasitic RC extraction. Then we proceed towards the STA and Physical Verification. This STA is Post-Layout STA. In physical verification we do IR Drop analysis, EM analysis,Antenna Rule Check etc. Next comes Formal verification and sign off.  

So in both analog and SoC Design DRC is equally important and a design be it analog or digital need to be DRC clean before going for fabrication.

Different Mask Layers :

                   Fig 2. Different Mask Layers in layout 

Now let's see what are the various mask layers are used to create layout on the silicon wafer. Layout is nothing but layout of the mask on the wafer. Each part is created with single mask . Metal layers like Metal 1, Metal 2, Metal 3, Metal 4 and we can go upto layers permitted in that particular technology node. Then we can have different types of Well (n and p)  and Poly (gate). Then we can have the contact as Cont layer and Via. Via is used to connect two metal layers in routing or BEOL stage and cont is used as source or drain contact.Cont is at FEOL layer. If you want to understand FEOL and BEOL in detail read our article on this topic. Then comes active

layers like ndiff, pdiff, nfet and pfet. Then select layers (n+ and p+) are also present there.

CMOS Fabrication :

                                                           Fig 3(a)  

 

                                                        Fig 3(b)  

                                                         Fig 3(c)  

Lets see how a PMOS and NMOS are fabricated and connected to built the CMOS. From above three figures we can see MOS is fabricated in layer by layer using different masks. Its done in batch process i.e, when Metal 1 is fabricated , it is done across the whole chip. Similarly all the other layers are fabricated. 

For PMOS there is N-well and P -select whereas for NMOS there is N-select. Inside N and P select  diffusion layers and Source and Drain contacts are created as shown in Fig 3a. Before creating contacts all the steps involved are in FEOL. After that Poly gates are created and connected with each other see Fig 3b. At final steps  Vdd, GND and Vout connections are created see Fig 3c. Connection between transistors , Source or  Drain contact creation and Poly gate creation and connection all are included in MEOL. Any step  beyond output contact creation is included in BEOL.

Sequence of Mask Layer : 

                                      Fig 4. Different Mask Layers  

Above figure shows how the mask sequence is introduced in the CMOS fabrication process. It is a typical example we are using to discuss the topic. The above figure shows the sequence starting from N-well, Poly, N+ diffusion, P+ diffusion, Contacts and then Metl layers. So this way sequentially the layers are picked up from the layout and fabricated on the Silicon wafer.

Design Rules :

Each semiconductor process step imposes a set of design rules on the geometric component size, relative position, etc. These rules have subtle differences however the common theme remains the same, mainly to use the proper geometric shape and separation to create a reliable manufacturing process. Some Rules are :

1. Intra-layer: widths, spacing , Length & Width of Transistor  gate

2. Inter-layer: enclosures, overlaps, Separation between 2 wires on same level

3. Width of wires

4. Contact pad for Vias, Well and substrate contacts

5. Cross section of Vias

6. Size of Wells

7. Area, antenna rules, density rules

Antenna rule is a separate topic. If you want to know in detail about Antenna Rule read this article  or watch video lecture here.

Classification of Design Rules :

If we classify based on unit, design rules are Micron rules and Lambda rules. On the other hand if we classify based on spacing,there are Inter-layer rule and Intra-layer rule.Inter layer rules are for two different layers regarding spacing between them and all. Intra-layer rules are for same layer segment .

1. Micron Rules : Here, the layout constraints, such as  minimum feature sizes and minimum allowable feature separations, are stated in terms of absolute dimensions in micrometers or nanometers.

2. Lambda Rules : Here, the layout constraints are expressed in terms of a single parameter λ. Hence allow linear and proportional scaling of all geometrical constraints.

So Micron rule is a absolute rule and lambda rule is a relative rule.

So lets summaries the whole discussion. 

So far we know,

1. All Design Rules are Predefined by Foundry. 

2. Design Rules are Available through Design Rule Manual (DRM) in text/ASCII format. 

3. Design Rules are Interpreted by Any Physical Verification 

 Tool through TCL Coding or Tool-Specific Propitiatory 

 Language. 

4. Layout Tools may have On-The-Fly Live DRC Check during layout Drawing. 

5. To understand any DRC Violation we need to cross-reference DRC-Rule-Code and DRM.

Find the video lecture on this topic here :

Courtesy : Image by Alexandre Debiève on Unsplash