Power supply noise and ground bounce can cause considerable path delay variations in VLSI Circuit. In any VLSI circuit Source and Ground are two power lines are present and noise in any of them will cause considerable delay in performance. Ground Bouncing noise is the primary cause of false switching in high speed circuits and a major cause of poor signal quality. Within a circuit multiple blocks are there and not all of them are in similar logic state all the time. Let's take an example where two adjacent block are there and one of them are in sleeping state or in between a transition. Since the ground and power lines are shared , during wake up event the bouncing noise generated in one power domain is transferred to the other block and can flip the logic states of the block. This noise is known as Ground Bounce Noise.
A major component of the circuit noise is the inductive noise. It is a critical and challenging design task to control the amount of inductive noise that is inserted into the power planes. Package pins, bonding wires, and on-chip IC interconnects all have parasitic inductance. When an inductor current experiences time-domain variation, a voltage fluctuation is generated across the
inductor. This voltage is proportional to the inductance of the chip-package interface and the rate of change of the current.As a result, when the logic cells in a circuit are switched on and off, the voltage levels at the power distribution lines of the circuit fluctuate. This inductive noise is sometimes referred to as the simultaneous switching noise because it is most pronounced when a large number of I/O drivers switch simultaneously.
Correlation of Power and Ground Bounce
Ground Bounce in Ground Noise. Power Bounce is Noise Glitch on Power Line. When Ground Bounce and Power Bounce are in Phase (Common Mode Noise) they will not effect the local logical cells but will degrade the signaling between two distant cells. Within a chip the metal connection runs for meters and meters if we sum them up. SO if we measure signal level in any two distant cell we might find variation in ground and power due to noise we discussed. When Ground Bounce and Power Bounce are out of phase (Differential Mode Noise), they adversely effect the local logical cells causing jitters in timing circuits.
Ground Bounce Mitigation Technique :
Many design techniques have been used to reduce the effect of ground bounce, such as :
i. Power Gating Technique
ii. Stacking Power Gating Technique.
iii. Various Multi Threshhold CMOS(MTCMOS) Technique.
iv. Adding Decoupling Capacitors (DECAP)
v. Having separate ground buses for I/O buffers and internal circuitry.
vi. Widening Ground Interconnect Buses
vii. Evenly distributing circuitry among many Power and Ground pins.
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