We have already discussed about basic level shifters in another article. Here in this article we will discuss about a little bit more complex and state-of-art level shifters. On completion of this article you will be able to answer below questions?
1. What are different state-of-art level shifters?
2. How does a cross coupled level shifters work?
3. What is a bootstrap level shifter and how does it work?
4. Definition and working principle of DCVS Basic Level Shifter.
5. Definition and working principle of DCVS Advanced Level Shifter.
Level Shifter Philosophy:
Fig.1 : Level Shifter
Among multiple voltage domains, threshold voltages are also different. In order to interface between the super-threshold, near-threshold, and sub-threshold cells, appropriate level shifters must be placed.
Level Shifter :
The level shifter is required because the logic high output of the sub-threshold gate does not meet the minimum logic high input of the super-threshold gate.
The three combinations that are required for the hybrid methodology include interfacing:
(i) sub-threshold to super-threshold.
(ii) sub-threshold to near-threshold.
(iii) near-threshold to super-threshold.
Clock Domain Crossings :
Fig. 2 : Clock Domain
Each clock domain/voltage island can be considered as individual layer/block. Number of clock/voltage domain crossings need to be minimized. Among multiple clock domains, all the scan cells of the same clock domain are tied together. All flops in the same clock domain are also grouped together. The number of inter-clock domain lockup latches are kept fixed.
Voltage Domain Crossings :
Fig. 3 : ASIC/SOC Design
In multiple voltage islands/blocks, logic level shifter is needed to calibrate the voltage change between different voltage of logic levels. Scan-chain design in DFT for multiple voltage islands also raises the power-sequencing issue.
One solution is that power-sequencing circuitry is held to the power-on state during test operation. Another solution is that each power-sequenced island is tested independently.
The combination of multiple clock domains/multiple voltage islands needs special consideration and attention.
Cross Coupled Level Shifter :
Fig. 4 : Cross-coupled Level Shifter
Conventional level Shifters are designed using cross-coupled P-MOSFETs. The incoming low voltage signal is inverted using an inverter connected to a low voltage domain (VDDL). Cross-Coupled PMOSFETs Transistors P1 and P2 are used to pull output to the high voltage (VDDH).
Boot Strap Level Shifter :
Fig. 5 : Boots Strap Level Shifter
In Bootstrapping technique transient power is reduced during level shifting. Two boot capacitors Cboot-1 and Cboot- 2 replace NMOS transistors to maintain the voltage difference at the gate terminals of P2 and N2. The pull-down NMOS N2 at the output stage is driven between 0 and VDDL whereas the pull-up PMOS is driven between (VDDH − VDDL) and VDDH. Bootstrapping technique achieves lower power at the expense of significant increase in physical area due to the relatively large boot capacitors.
DCVS Basic Level Shifter:
The DCVS level shifter operates as follows. In beginning, IN = 1 and IN = 0 , OUT = 1 and OUT = 0 . Then transition happens as IN = 0 and IN = 1 , the NR goes off OFF and NL goes ON. PMOS PL remains at 0 V, maintaining PL on to resist the NL transistor by simultaneously charging node out. NR and NL is connected to the low input signal (realted to VDDL) & operate in cut-off region. Gates of PR and PL is connected to the high voltage supply. NL and NR struggle to sink more current than the PMOS pull-up transistors source. If NL sinks greater current than the PMOS pull- up transistor sources, node OUT discharges.The PR transistor toggles from the OFF state to the ON state, and charges node OUT. This cuts off the pull-up transistor PL, completing the transition.
DCVS Advanced Level Shifter:
When the differential input is sufficiently shifted, the significantly stronger NLT and NRT transistors complete the transition. PMOS PLT and PRT are controlled with corresponding input voltage to limit the current flowing through the full voltage pull-up transistors, PL or PR. For high input IN/IN, PLT/PRT is fully ON , providing the desired charging current. PRT/PLT limits the current, allowing the NMOS pull-down network NR/NL and NRT/NLT to discharge the OUT/OUT node.
Now lets summarize what we have discussed above ;
A level shifter ( a.k.a voltage level translator or logic-level shifter ), in digital electronics, is a circuit used to translate signals from one logic level or voltage domain (VDD/VSS) to another. It allows compatibility between different sub-chip blocks of ICs with different voltage requirements, such as TTL and CMOS. In VLSI most common logic levels have been 1.8V, 3.3V, and 5V. However levels above and below these voltages are also used. Advanced Level-Shifters such as Cross Coupled LS , Boot-Strap LS , DCVS LSetc are used as modern day level shifters.
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