In this article we will discuss about basic level shifters, their importance and working principle. Once completed you will be able to answer the below questions:
1. What is a level shifter?
2. How does a level shifter work?
3. What are different source and sink position of a level shifter?
4. What are different variants of level shifter?
In modern ASIC-SOC design, different design blocks like digital, analog, macros are fabricated on a single chip and need different supply voltages for optimum performance, efficiency and speed. In multi voltage domain (i.e multi power domain) system, the logic gates on noncritical paths are operated with low VDD(a.k.a VDDL) and gates on critical path are operated with high VDD (a.k.a VDDH). Chip with different supply voltage domains use level shifters to convert and propagate logic signals among different power domains. When a logic ‘1’ signal of VDDL block drives the VDDH logic gates block, the PMOS of VDDH operating logic gate blocks may not become perfectly ON rather may lie between partially ON and weakly ON states. The level shifters are inserted at proper domain crossings to change the voltage levels accordingly to mitigate the above situation. Also level shifters are inserted between core circuits and I/O circuits in multi-power domain chips.
Conventional Level Shifter Operation:
The circuit diagram is a conventional level shifter thatconverts the logic level ’1’ from VDDL to VDDH.
When '1' (VDDL) is applied to the input :
1. P5 goes OFF and N5 turns ON resulting output '0'.
2. This '0' at node T5 is applied to N1 and turns it OFF.
3. It is also goes to Inverter T4 which makes P4 ON and N4 OFF.
4. The output of T4 is now '1' and is applied to N2 thus turning it ON.
5. N2 now pulls down T2 to '0'.
6. This turns ON P1 which, in turn, pulls up T1 to '1'.
7. T1 is connected to the gate of P2 which now gets turned OFF.
8. T2 remains at a value '0' which turns ON P3.
9. P3 pulls up the value of OUT to logic ’1’ (VDDH).
Level Shifter Standard Cells :
Fig 3 : Placement of Level Shifters
When two blocks powered with different voltage levels interact with each other, invalid signal transmissions and crowbar current generation may take place. To avoid this, level shifter cells are placed between the blocks with distinct voltage values. Level shifter cell can convert a high voltage level to low voltage level between the domains. Level shifters are the placed on signals that have sources and sinks operating at different voltages.
Positioning of Level Shifter Cells:
Fig. 4: Positioning of Level Shifter
Level Shifter POSITION defines where the level shifter cells are placed in the logic hierarchy. All necessary supplies need to be available in the specified location.
i. Self : The level shifter cell is placed inside the model/cell being shifted.
ii. Parent : The level shifter cell is placed in the parent of the cell /model being shifted.
iii. Sibling : A new sibling is created into which the level shifter cells are placed.
iv. Fanout : Level shifter occur at all fanout locations (sinks) of the port being shifted.
v. Automatic : the implementation tool is free to choose the appropriate locations.
Level Shifter Variants:
i. Uni-Directional : All input pins are dedicated to one voltage domain, all output pins are dedicated to the other.
ii. Bi-Directional with Dedicated Ports : Each voltage domain has both input and output pins, but the data direction of a pin does not change.
iii. Bi-Directional with External Direction Indicator : When an external signal is changed, inputs become outputs and vice versa.
iv. Bi-Directional with Auto-Sensing : A pair of I/O spanning voltage domains can act as either inputs or outputs depending on external stimulus without the need for a dedicated direction control pin.
Well that was all about basic level shifters and lets summarize what we have discussed:
A level shifter (a.k.a voltage level translator or logic-level shifter ), in digital electronics, is a circuit used to translate signals from one logic level or voltage domain (VDD/VSS) toanother. It allows compatibility between different sub-chip blocks of ICs with different voltage requirements, such as TTL and CMOS. Modern systems use level shifters to bridge domains between processors, logic, sensors, and other circuits. In VLSI most common logic levels have been 1.8V, 3.3V, and 5V. However levels above and below these voltages are also used. A level shifter increases the total area of the circuit, which in turn, increases the power dissipation. If voltage levels are far apart, the level shifter design becomes complex and error prone.
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