In this article we will discuss about decoupling capacitor or DECAP. Once completed you will be able to answer following questions:
1. What is decoupling capacitor and why it is important?
2. Basic construction of CMOS DECAP?
3. What are on-chip and off-chip DECAP in vlsi?
Decoupling Capacitor(DECAP) :
A decoupling capacitor(DECAP) is a capacitor used to decouple one part of an electrical network (circuit) from another. Both off-chip and on-chip DECAPs are used in VLSI. We will restrict out focus on On-Chip DECAPs In this discussion. As per circuit theory (KCL/KVL) , if the voltage level for a device is fixed, changing power demands are manifested as changing in current. When the current draw in a device changes, the power supply respond to that with a transient change. Such noise caused by circuit elements is generally shunted through the DECAP, thus reducing the effect of the noise on the rest of the circuit.These DECAPs have to be manufactured into the chip and their placement hasto be decided at design time.
Importance of Proper Decoupling :
For high performance(freq) digital ICs, such as ASIC and FPGAs, the allowable tolerance on the supply (typically ±5% ) includes the sum of the dc error, ripple, and noise. The digital device will meet specifications if this voltage remains within the tolerance. So, it is necessary to keep high frequency noise from entering the chip in the first place. This is generally done with a combination of electrolytic capacitors (for low frequency decoupling), ceramic capacitors (for high frequency decoupling), and possibly ferrite beads. All decoupling capacitors must connect directly to a low impedance ground plane in order to be effective.
Types of DECAPs:
Capacitors between power and ground networks are referred to as DECAPS or decoupling capacitors. There are two types of decoupling capacitance in a Power Delivery Network (PDN):
i. Intrinsic Decap: Parasitic capacitance between the the metal interconnects of the supply lines, device capacitance and the capacitance between substrate and N-well are the intrinsic decap. The intrinsic decoupling capacitance is not sufficient to constraint the voltage drop within prescribed safe limits. So, designers have to add explicit DECAP on the die at supply points.
ii. Extrinsic Decap: The explicit DECAP added occupy more area and consume more power in a chip.
Positioning of DECAPs in a CHIP :
Fig 1 . Different types of DECAPs in whole chip
In side the whole chip different types of decoupling capacitors are used, not all of them are standard cell DECAPs. Above figure shows different types of decaps, such as,
i. Bulk DECAPs,
ii Mother Board (MB) DECAPs,
iii. Package DECAPS,
iv. On-DIE DECAPs
On Chip DECAP:
Simplest form of DECAPs are basically NMOS transistors.Top plate is polysilicon, bottom-plate is inverted channel, insulator is gate oxide. To make the DECAP, you connect POLY to VDD and source/drain to VSS. Generally Standard Cells Library contain necessary DECAP cells. Adding decoupling capacitors (decap) between the power network and the ground is an effective and widely adopted approach to reduce the power network impedance and therefore reduce the power network noise.
DECAPs & Physical Design
Optimization with DECAP has two stages. The first stage is to pre-place DECAPs before placing the standard cells.The second stage is a post-placement refinement to the existing floorplan in an incremental manner. In the post placement refinement DECAP placement is done to meet both IR-drop and also power related circuit timing targets. When DECAPs placed far away from noisy nodes, it lead to insufficient noise reduction. An optimal placement of DECAPs has to be done in standard-cell based ASIC design for proper noise reduction.
FPGA and DECAPs :
FPGAs have current consumption profile which is unknown at design time. The mapped designs decides the current consumption profile of the chip at configuration time. Hence a large number of on-chip decaps are necessary to achieve robust power grid design in FPGA catering to different designs mapped onto it. Consequently there will be more unused on-chip DECAPS in that part of the FPGA where a design is not mapped. These unused DECAPS have leakage overheads associated with them and the leakage power for these DECAPS is expected to rise exponentially with reduction in oxide thickness.
Decoupling Capacitor using NMOS:
Fig 2 . n-MOS DECAP
A standard decap is usually made from NMOS transistors in a CMOS process. The gate of the NMOS transistor is connected to VDD. The source, drain and substrate of the transistor are tied to VSS. This approach is considered effective because the thin-oxide capacitance of the transistor gate provides a higher capacitance than any other oxide capacitance available in a standard CMOS fabrication process.
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