1. Electrostatic Discharge (ESD) :
In the most simplistic word , Electrostatic Discharge (ESD) is the release of stored static electricity. The most famous type of ESD (large scale) is lightning which voltages up to 10^7 V and currents up to 30 kilo-amperes. Electrostatic charging of two objects results from electron transfer during friction. ESD is the electrostatic event which balances the charge potential difference between two charged objects with opposite polarity and leads to a high current for a very short time.
The incident of lightning we can see with our bare eyes whereas the ESD event that take place in chip is not visible. On an average ESD destroys about 20 % of electronic components before they are installed into a system. After assembly, anywhere from 33 to 70 % of digital devices fail soon after customers purchase because ESD may only damage a component but it opes the door to further subsequent damages within a brief time during circuit operation.
A person can acquire charges by simply walking across a room. When such a charged person or object then approaches a grounded conductor, for example a pin of a packaged Integrated Circuit (IC), an Electrostatic Discharge (ESD) event occurs, characterized by a high current ( ∼ A) within a few ns. A high current density and/or electric filed can damage conductor, semiconductor and insulator in an IC.For this reason electrostatic straps are used in industry where electronics circuits are packaged and assembeled.
A human's sensory perception cannot recognize the several thousand volt discharge of ESD.
The circuit present inside the IC, will tend to be partially damaged or might breakdown when this high voltage pulse enters. When we buy different semiconductor component for computers we get it in a dark grey package , that is basically a external protection for ESD event. In this article we will talk about internal protection for ESD.
2. ESD Damage & Protection :
ESD in an IC is usually start with the oxide breakdown which result in percussion path. The high current density damages the semiconductor devices through thin-film fusing,filamentation, and junction spiking. The high electric field, on the other hand,can cause failure through dielectric breakdown or charge injection. Dielectric is used in an IC for MOS structure, isolation etc. ESD can damage any dielectric in IC. Hence necessary components are used to protect ESD so that the destruction of a product or system when touched can be eliminated. Due to this factor, there is a strict packaging, handling and design requirements on suppliers by Govt and many other companies. The below picture shows typical I/O schematics protected by ESD cells. Vdd, Vss, I/O Pads are actually connected to IC periphery. Core of the circuit is shown in the middle and Clamp is on the other side. This a typical arrangement of ESD protection scheme. 
Fig 2. ESD stack diode
3. Various ESD Damages :
Lets discuss some damages take place due to ESD event.
i. Junction Burn Out :
Junction Burnout is caused by the injection of an ESD transient of sufficient energy and duration to force the junction into secondary breakdown. Junction burnout is often characterized by high reverse bias leakage current or a total short.
ii. Oxide Punch-Through :
Oxide punch-through is the other major category of ESD damage. Oxide punch-through occurs when an oxide is subjected to an ESD pulse of a high enough magnitude to cause the oxide to breakdown. Transient domain of an ESD event, the voltage applied the gate oxide must be very large to initiate oxide breakdown.
iii. Metallization Burnout :
Metallization burnout is often a secondary effect, occurring after the initial junction or oxide failure took place. Metallization burnout occurs if the current flowing through the metal forces the temperature to rise, due to the I2R power calculation, high enough to reach the melting point of the material.
4. Characteristics of a good ESD protector :
A good ESD protector must -
i. Clamp the ESD voltage to shunt the ESD stress current
ii. Turn-on fast enough
iii. Can carry large currents
iv. Have low turn-on-resistance and minimum series resistance
v. Occupy minimum area at the bond pad
vi. Have minimum capacitance
vii. Standout robust against for numerous pulses
viii. Not interfere with IC functional testing.
5. ESD Protection In VLSI Design :
ESD Design Rules:
The protection design implementation becomes complicated for different I/O signal configurations. Also, placement of unrelated circuits near an I/O pad causes unexpected current paths through interactions and may render the protection device ineffective. The same could occur in the internal connections between the power supplies, preventing the power supply clamp from operating. All of these issues are covered in ESD design documents so that product ESD design is addressed properly from the beginning.
ESD Protection is done using several types of IO Cells such as:
i. Digital I/O Buffers : Provide High drive up-level shifting output. Provide down-level shifting and ESD protection for inputsii. Analog I/O Cells : Provide ESD protected analog inputs/outputs
6. ESD Protection Methodology :
The main goal of ESD protection circuits is to provide a low-resistive discharge path. Figure shows the typical chip-level ESD protection scheme in which an ESD power supply clamp is connected between the two power rails under different ESD stresses. The ESD clamp provides the discharge path for an ESD event that happens between the two power rails.
Clamps could be of category:
(i) Static clamps (ii) Transient clamps.
The static ESD clamps turn on once the voltage across the supply rails exceeds the triggering voltage and start conducting the current of the ESD event.
The transient ESD clamps take advantage of the rapid change in voltage during an ESD event to trigger the clamp using a rise time detector and a delay element to keep the clamping element on during the entire ESD event. Transient clamps are able to react fast; however, these circuits must be carefully designed to keep their leakage to minimum.
7. ESD Protection Schemes :
i. Diodes
Turn-on Type Device (Zener Diodes):
A turn-on device like diode turns-on after reaching a particular trigger-voltage.
Once the device is turned-on, it offers a low impedance path for the ESD current to flow.
The Current-Voltage (IV) characteristic for such a device is shown in Figure. Diodes offer
a simple and effective turn-on type ESD protection. They can be used in either the forward-biased
or reverse-biased configuration since diodes have the I-V characteristics as shown in Figure.
They offer a low resistance path. The advantage of this method is that it can be simulated using SPICE. One limitation is the fixed diode turn-on voltage which can reduce the application of the diode for this.
8. Stack Diodes :
Figure shows an ESD protection structure consisting of stacked diodes. Under normal operating conditions, the diodes are reverse biased and hence in the off-state. During an ESD event, the diodes forward bias and divert the ESD-induced current away from the internal circuit. The drawbacks of such a structure include the relatively large on-state resistance and added complexity in optimizing the interconnect metallization parasitic for advanced CMOS process technologies.
9. Snapback Type Devices :
Snapback type protection schemes are capable of handling higher currents.
Grounded-gate NMOS (ggNMOS), gate-coupled NMOS (gcNMOS), SCR (Silicon controlled rectifier) are ESD protection devices which work based on snapback mechanism.
5 Different Types of SCR are used for ESD protection:
i. Low-Voltage Triggered SCR (LVTSCR)
ii. Gate-Coupled LVTSCR
iii. Substrate Triggered SCR (STSCR)
iv. Double Triggered SCR (DTSCR)
v. Boundary MOS Triggered SCR
10. Silicon Controlled Rectifier (SCR) :
SCR which provide the high value of the area gain factor compare with other protection structures.
SCR is commonly used for ESD protection in advanced processes technology.
However, a SCR has high triggering voltage of approximately 20V compared to low holding voltage about 1~2V. SCR is popular for its area efficiency: with same ESD protection level SCR occupies smallest area among the three basic devices. The cross schematic view and the equivalent circuit of a SCR are shown in Figure, in which consisting a PNPN structure. After trigger, the SCR will exhibits a snapback I-V characteristics as shown. Typically, SCR has large snapback.
11. Gate Grounded NMOS (GGNMOS) :
To solve ESD problem, GGNMOS (Gate Grounded NMOS) is commonly used in protection device. GGNMOS is easy to design and is perfectly compatible with CMOS processing.
However, it consumes relatively large silicon area because of the low current driving capability.
Due to GGNMOS has simple structure and it is compatible with CMOS technology, it is also a popular device in ESD protection. GGNMOS is modified from the normal NMOS device.
In GGNMOS, the drain of NMOS serves as the anode, and the shorted gate, source and body contact are tied together to serve as the cathode.
12. ESD Protection Schemes : Clamp
ESD Protection Circuit :
There are different on-chip protection methods used for ESD protection. The rail-based ESD protection circuit is one among them. Placement of the power supply clamps determines the effectiveness of the IO protection in a rail-based ESD protection arrangement.
Power Clamp :
Power clamps are present inside each power supply IO. They are used to shunt current to ground from power supply lines when an ESD event occurs or any event which can potentially damage the electronic components. The RC-triggered power clamp is a simple and efficient implementation to achieve the same.
Courtesy : Image by Philippe Donn from pexels
