Power Management Methods:
In a state-of-art chip power management inside the IC is done in several different ways. Lets take a brief look on such methods. First in the list is using multiple threshold voltages or Multi Vt. Next comes using multiple VDDs for multiple domain in the same chip. We use power gating method for managing the power between two different blocks in the same chip. We use clock gating for clock cells. Dynamic Voltage scaling and Dynamic Frequency Scaling are two other methods used for power management. Different standard cells like Retention Flop/Cell , Isolation Cell , Power Switch Cell, Level Shifter Cell are used for power management in a chip.
Introduction to Retention Concept:
Fig. 1 : ASIC/SOC Design
When a Device/Circuit is inactive for a long period of time, a “Snooze” button helps to save the battery. Memories or registers are not capable of keeping their information while powered off. When a particular power domain inside chip is switched off, it is bound to loose its memory. To save such scenarios special retention cells have been adopted in most of the commercial standard cell libraries (eg. TMSC, UMC, GF), to support the State retention power-gating (SRPG). Retention cells store the last state before power off of a flop inside the power domain. Thus it allows the system to continue its operation from the last known state and faster wake up of a block. The only Drawback is the Retention Mode consumes little more current than power off mode.
Retention-Cell/T-Latch/Retention-Flops :
Retention Cell has a flip flop and a state saving latch. Supply of flip-flop is switchable and latch is always on. The latch associated with it will retain the prior state when its power is off. The multiplexer allows us to save and restore the logic in latch. A retention cell consists of a flipflop and a save latch and has two control signals, SAVE and RESTORE. SAVE signal indicates when the data should be saved in the latch, which is just before Switching OFF the power. RESTORE signal tells when the data stored in latch should be restored which is when the domain gets back to active state.
Under Power Gating comes Power Shut Off (PSO) where un- utilized blocks are switched off completely to stop any leakage current. PSO is triggered for any block whenever it goes to standby mode. It should be verified along with working RTL ensuring that the entire chip operates flawlessly whenever any such powered off block is turned on again.
State Retention Power Gating (SRPG) :
To implement PSO, state retention cells are bare necessary to store existing state of the blocks before it is shutdown. During synthesis is isolation cells, retention cells, level-shifter cell and
always-on cells are inserted automatically based on CPF/UPF description.
Retention Cell in Front End Simulation & Verification :
When the verification environment launches test cases during simulation different power states are entered. The modules in the supply network propagate their state through out the network. It generates the power management signals:
a) enable the Power Switches and of the Isolation cells.
b) save the State in Retention cell (to store registers values before their shutting off).
c) restore from State Retention cells (to retrieve registers values once switched on).
Retention Cell in Back End (Physical Design):
While the system is created, the power design is coded in UPF/CPF. Power switches to change domain supply states are created. Power domains are described and connected to the supply network. After the floor-plan completion, all its specifications are dumped onto a Design Exchange Format (DEF) file. The inputs to the placement tool are the gate-level net-list, floor-plan DEF file, power intent file, timing module files, and reference library files. Sanity checks are performed on the floor-plan file and gate-level net-list. The power intent file is checked and any violations between the floor-plan data, gate-level net-list, and power intent are corrected. The floor-plan information is then loaded onto the Back-end EDA tool. Next, the power intent is committed, which adds the isolation cells, retention cells, enable Level Shifter, and Power Multiplexers.
Types of Retention Cell Latch :
Balloon Latch
Master-Slave Latch
Balloon Type Retention Cell :
In a “balloon” type retention register, the retained value is held in a shadow or additional latch, often called the balloon latch and usually powered by the -retention_supply. A “balloon” type retention register typically has additional controls to transfer data from a storage element to the balloon latch, also called the save stage. And transfer data from the balloon latch to the storage element, also called the restore stage. The ports to control the save and restore pins of the balloon-style retention register need to be available in the design to describe and implement this type of retention registers. The balloon element is not in the functional data-path of the register.
Master-Slave Type Retention Cell :
A master or slave-alive retention register, the retained value is held in the master or slave latch and also powered by the –retention_supply. In this case, the retention element is in the functional data-path of the register. A “master or slave-alive” type retention register typically does not have additional save or restore controls as the storage element is the same as the retention element. Additional control(s) on the register may park the register into a quiescent state and protect some of the internal circuitry during power-down state, and thus the retention state is maintained. The restore in such registers typically happens upon power-up, again owing to the storage element being the same as the retention element. Thus, this style of registers may not specify save and (or) restore signals, but may specify a retention condition that could take the register in and out of retention state.
Now lets summarize what we have discussed :
Retention cell is an integral part of the present Standard Cell Library used in ASIC Design. It is a must for the chips where there are multiple Power Domains are existing. In the Power Aware RTL design retention cell is equipped through UPF/CPF. There are two major types of the Retention Cell : Balloon Type and Master-Slave Type.
Watch the video lecture here:
