IP Views :
When we receive a design kits there weill be different files with various extensions. We need to know which file is required for which tool. Here we will talk about front end Rtl views, front end timing views and also backend views like Layout Views, Physical verification views Phy-Ver Views, Parasitic extraction Views and finally Compiled Macro Views.
Each Different EDA Design Tool requires specific format of input files and they generate specific output file with particular file format. All proprietary tools have their own file format and file meant for one tool is not compatible to any other tool. The same unit cell , while passing through various stages of design requires specific format as per the stage. EDA Tools have their propitiatory format for each unit cell or block of the design. This restricts a end-user to stick to same-vendor and this is a business move rather than technology need. Most big houses use multiple commercial tools meant for same work (obviously from top competing vendors) for a step. So in such case multiple files are required with different extensions for same step.
Front-End Views :
1. RTL :
Verilog and VHDL views are two most common and popular views in front end. For assertion and and other capabilities system verilog view is most important. For every unit cell all types of definition with proper extension is available in the library. DB,SDB, SLDB are also some front end views. Here mentioned *.db, *.sdb and *.sldb all three are is Synopsys database format.
Other front end views include UPF (Unified Power Format) , CPF (Common Power Format), OA (Open Access) etc. We have a playlist on UPF. You can watch here.
2. Timing views :
Timing views are contained in the .lib files. There will be corner wise variation like fast-fast, slow-slow, typical-typical etc. We all know in PVT (power, voltage and temperature) there are three corners like slow,fast and typical. In the .lib files there are variations of how the look up table are taken care of .Different timing models are there and as well the extension of the lib files are different like *.ocv, *.nldm, *.ccs, *.ecsm , *.nldm , *.ccs, *.ecsm are basically timing models.
nldm stands for non-linear delay model
ccs stands for concurrent current source
ecsm stands for equivalent current source model
ocv stands for on chip variation
aocv stands for advanced on chip variation.
3. Transistor Level Views :
*.cdl and *.spice are two different extension of files with transistor level data. Generic transistor level netlist is SPICE or CDL. Both are representation of a circuit with transistor level data. Specific tool compatible view could be HSPICE or ELDO or SPECTRE.
Back End View :
Now lets talk about back end view. Back end covers all the steps between syntheses ans tape-out. All the layout, timing, physical verification are done at back end so the number of back end views are higher when we compare them with front end views.
1. Layout Views :
The layout views are created with layout editors. The first file we can find in layout view is mapping files. These mapping file generally contains various layers and numbers. NDM,DB, GDSII are other layout views. Synopsys tools use *.db files. Whereas Cadence tools uses *.lef and *.def files. OASIS view is much more generic view. There could be CIF files and abstract view. The design kit can contain some of them, many of them or all of them. How many files would be there in the kit depends on which tool or tools are used.
2. Physical Verification Views:
Some most popular physical verification tools are Voltus, Redhawk, Asura, Calibre, Herculis, ICV etc. Depending on the design need and customer demand a design house could use multiple of them. So the design kit contain views and files compatible to the tools.
3. Parasitic Extraction (PEX) Views:
Some parasitic extraction views are *. spef, *.dspf and *.sbpf.
SPEF stands for Standard Parasitic Extraxtion File
DSPF contains transistor level parasitic extraction data and generally compatible to SPICE tools
SBPF is a binary format and used by Synopsys tools.
4. Macro Views :
More generically these are called compiled macro views. The word compiled is used as there are compilers that compile these views. NVM, SRAM, DRAM etc. Are some semiconductor memories that might have compiled macro views.
Now lets summarize what we have discussed so far. Views are basically file formats. They are used to felicitate as many as tools possible. Variation of views may be different from one technology node to another technology node. No of views may vary from one standard cell vendor to another. Same view of associated with a particular tool may become incompatible over time due to fabrication-technology related changes inside the tool. So always use the latest library with up-to-date version of the views.
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