Chiplet Based IC Design

Chiplets are a hot topic in the semiconductor industry now. According to many multi chip module and SiP or System in package are game changers. Its a paradigm shift for designers and consumers. In this article we will discuss about chiplet and chiplet based design, their advantages and challanges. 

Chiplet :

A chiplet is a tiny integrated circuit with subset of total functionality and designed to work along side many other similar chiplets to form larger chip with complex functionality. A set of chiplets can be implemented in a mix-and-match fashion and that approach has several advantages over a traditional system on chip.  Chiplets are usually reusable IP blocks. Chiplet is a hot topic in VLSI now and  Chiplet based design has already hit the market.  AMD’s Ryzen, Ryzen Threadripper & Epyc CPUs are based on the company’s Zen architecture, examples of retail-ready products that contain chiplets.

Fig 1 : Chiplet based design

Monolithic vs. MCM :

Fig 2 : Monolithic vs. MCM

In a monolithic IC , many functions are built on same silicon whereas in a chiplet based design, multiple chiplet , each with smaller subset of bigger functionality and feature are integrated together to form a more complex and bigger system to achieve bigger functionality and list of features.  Such an assembly is called  MCM (multi-chiplet module). MCM does not have to be a complete system rather it’s a tightly coupled subsystem or module in a package. 

Advantages of MCM : 

Chiplets can be designed in the optimum process node (performance, power, cost) for the particular function and/or feature Size and yield. When Monolithic Si has reached its limit and chiplets are much easier and cheaper to manufacture. Chiplet based design allows integration of potentially incompatible semiconductor materials, such as GaN, SiC etc on same system. Chiplets can be re-used over multiple products and projects. Designer can select the right combination of chiplets for their needs.  Non recurring engineering cost is less for chiplet designs. 

Various MCMs :

                             Fig 3 : Various MCMs

There are two types of MCMs :  

i.  Homogeneous ,

ii. Heterogeneous.

Homogeneous MCMs, contains chiplets from only a single chip maker. An example would be AMD Ryzen Zen 3 processors.

Heterogenous chiplet MCM contains chiplets from multiple manufacturers, often made in different facilities on different process nodes. Heterogenous MCM might include a combination of CPU, GPU, NPU, FPGA,  and/or special purpose chiplets. Chip consumers can assemble the optimum selection of chiplets into a heterogenous chiplet MCM for their needs, and  chiplet suppliers can manufacture their chiplets in the ideal location/node for price, performance, and area.

Heterogeneous Integration:

                         Fig 4 : System-In-Package

Heterogeneous Integration is integrating individually designed, and fabricated components. Those components are assembled on the substrate layer called interposer. The final objective is to develop a system which perform a function like an SoC. Such a a higher-level assembly called System in Package (SiP). SiP can be a vertical stacking (3D) or adjacent placement (2.5D) of chiplets on the substrate layer called an interposer. Intel Agilex, AMD EPYC are the commercially available heterogeneous 3D SiP.

SiP provides greater functionality and achieves better-operating characteristics which are challenging to achieve on a single die SoC.

Motivation for Heterogeneous Integration :

                             Fig 5 : 2.5D and 3D package

Heterogeneous Integration offer technical, functional and material diversity.  Chiplets are used from a matured process node so the development cost of SiP is reduced. Due to the incorporation of known good dies (KGD) manufacturing yield is high.  Moreover post-silicon validation is rarely required. Since Moore’s law has reached its limitation, increasing Functional density instead of scaling of transistor could lead to better performance.  Innovations in packaging and design like heterogeneous integration is very promising in this context. With 3D packaging technology, CPU and memory dies can be stacked, allowing increased memory bandwidth and decreased transmission latency as the dies have much shorter interconnects.  The 2.D and 3D packaging paradigms have led to smaller area and size requirements.

Challenges of Heterogeneous Integration:

Fig 5 : Challenges of Het. Integration

One big challenge in SiP design is the interfacing of chiplets due to the variety of chiplets and I/O interfaces. Ultra Short Range serdes is suitable for high-speed inter-connection in Die-to-Die communication via 2.5D and 3D packaging technologies.  Although the transmission distance of USR hinders the large-scale integration of chiplets. Universal Chiplet Interconnect Express (UCIe) is an open industry standard interconnect that provides chiplets with high-bandwidth, low-latency, power efficient, and cost-effective on-package connectivity. Heterojunction Integration can increase the overall power density of the SiP, which can, in turn, increase total package power dissipation. Power is generally dissipated as heat, and it can increase thermal cross-talk, and temperature-sensitive components need further thermal isolatio.  Since chiplets are sourced from different makers, a question arise who takes ownership in root  cause analysis and fixes once sold to third party. That a concern from business point of view.  Secure Heterogeneous Integration is a concern.  Security both at Chiplet and interposer level is required. Strong security policy can protect integrity and confidentiality of any IP.   

SoC vs. SiP:

                                   Fig 6 : SoC vs SiP

Courtesy : Image by www.pngegg.com