In this article we will discuss about different types of delays in vlsi circuits. Once completed you be capable to answer below questions:
1. What are Cell, Path, Net, Input, Output, Exit and Transition Delay?
2. What is clock latency? What are different types of latency?
3. What are different types of clock skew?
4. What are different types of Jitter?
Cell/Gate/Propagation Delay :
Gate delay or Cell delay or Propagation delay is defined as the time required in transmission of signal through the gate. Signal transmission is not instantaneous and there is finite time gap between the signal applied at the I/P of the gate and response of that input found at O/P of the gate. Propagation delay for rising and falling edge are not same.The propagation delay (tp) is defined as average of tpLH, tpHL , i.e, tp= tpLH + tpHL.
Where, tpLH = response time of the gate for a low to high output transition while input switching from high to low tpHL = response time of the gate for a high to low output transition while input switching from low to high.
The delay is usually calculated at 50% point of input-output switching.
tr = Rise time = time it takes for the leading edge of a pulse to rise from its minimum to its maximum value. Rise time is typically measured from 10% to 90% of the value.
tf = Fall time = time it takes for the falling edge of a pulse to fall from its maximum to its minimum value. Fall time is typically measured from 10% to 90% of the value.
Clock Delay/Latency :
Clock delay or latency also known as Cock Insertion Delay. Defined as the amount of time taken by the clock signal in traveling from its source to the sinks. Clock latency comprises of two components : (1) Clock Source Latency, (2) Clock Network Latency.
Clock latency = Source latency + Network latency
i) Clock Source Latency/Source Insertion Delay: Defined as the time taken by the clock signal to reach the clock definition point from clock source ( PLL/Oscillator/some other source) . Also known as Source Insertion Delay.
ii)Clock Network Latency/ Network Insertion Delay: Defined as the time taken by the clock signal in traversing from clock definition point to the sinks of the clock.
Above diagram shows latency in presence of generated clock.
Generated Clock : A generated clock is derived from a master clock. A master clock is a clock defined using the create_clock specification. When a new clock is generated in a design that is based on a master clock, the new clock can be defined as a generated clock.
Pre CTS Latency and Post CTS Latency :
Latency is the summation of the Source latency and the Network latency. Pre-CTS estimated latency is considered during the synthesis and after CTS propagated latency is considered.
Transition Delay :
Defined as the time taken to change the state of the signal. Time taken for the transition from logic 0 → 1 or 1→ 0. Expressed as rate of change of logic or the speed of transition. Also Termed as known as "Slew".
Clock Skew :
Clock skew is defined as the difference of the insertion delays of two flops belonging to the same clock domain. Every component add some delay in signal transition. Clock signal take finite time to travel from one point to another so there is time difference between arrival of clock signal to two different flipflops. Difference between arrival of clock of two flipflops is skew. Skew can be local and Global and skew Value can be positive or negetive.
Two types of skew depending on positions of flops: 1) Local Skew , 2) Global Skew
Local Skew : Local skew is the difference of insertion delays of two communicating flops of same clock domain.
Global Skew is the difference between the delay times for earliest clock reaching flip-flop and latest clock reaching flip-flop for a same clock-domain.
Positive Skew: If the capture flop receives clock signal late than the launch flop than it results in Positive Skew.
Negetive Skew : If the launch flop receives clock signal late than the capture flop than it results in Negetive Skew.
Jitter :
Clock Jitter is defined as the deviation of a clock edge from its ideal position in time. Clock jitter is uncertainity in the clock edge. The cause may be noise, a fluctuating power source, or interference from nearby circuits. Jitter can occur in both direction, positive and negetive. Can be modeled by adding uncertainty regions around the rising and falling edges of the clock waveform. Clock jitter can be cycle-to-cycle, period jitter, long term jitter.
Cycle-to-Cycle Jitter: Signifies the change in clock period across two consecutive cycles. In t2 and t1are successive clock periods, then cycle_to_cycle_jitter = (t2 – t1).
Period Jitter : Difference between the ideal clock period and the actual clock period. Measured with respect to ideal clock period.
Long Term Jitter : Long term Jitter is the deviation of the clock edge from its ideal position. For a clock with period 20 ns, ideally, clock edges should arrive at 20 ns, 40 ns,60 ns etc. If nth edge comes other than at 20*n ns, there is long term jitter for nth edge and that is equal to= (20*n – 200) ns.
Half-Period Jitter :Half-Period Jitter is the measure of maximum change in a clock’s output transition from its ideal position during one-half period.
Path Delay :
Defined as the minimum time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin. Delay assigned to paths from each input to each output. Also known as pin to pin delay.
Net Delay/Wire Delay:
Input delay :
Input delay is the time at which the data arrives at the input pin of the block from external circuit with respect to reference clock.
Output delay : Output delay is time required by the external circuit before which the data has to arrive at the output pin of the block with respect to reference clock.
Exit delay : It is defined as the delay in the longest path or critical path between clock pad input and an output. It determines the maximum operating frequency of the design.
