Basics Of VLSI Interconnects:
Active devices and regions in IC are electrically connected to each other to make circuit. They are also connected to the outside world through their I/P and O/P on bonding pads. Contacts, vias and interconnects used for such connections. Contact is connection to source, drain or poly. Vias are connections between interconnect levels. Interconnects are separated from each other by dielectric layers. Dielectric layers separating global interconnect levels are called IMD/intermetal dielectrics or ILD/interlevel dielectrics. Vias connect interconnects through these layers. These components are part of the metallization/backend/BEOL.
VLSI technology moving to lower technology nodes. Device dimensions of interconnects scales down, by a factor called as ‘scaling factor (S)’. This scaling factor is an integer. The resistance, capacitance and inductance are affected by scaling.
Chip surface doesn't have enough space for all connections, so vertical interconnects are built. Number of metal layer increases with IC complexity. Aluminum interconnects were used as the standard for a long time in chip-making. In the late 1990s, chip-makers switched to Cu because it conducts electricity better than Al. Cu interconnects improved IC performance and can match transistor scaling.
VLSI Interconnects: Local & Global
There are two major types of interconnects Interconnects , Local & Global. Local interconnects are the first/lowest level of interconnects. They connect gates, sources and drains in MOS technology and emitters, bases, and collectors in bipolar technology. Local interconnects are small and short. Poly Si, Silicide, TiN, W (Tungsten) can act as local interconnect. Local interconnects can afford to have higher resistivities since they do not travel very long distances. But they must also be able to withstand higher processing temperatures. Global interconnects are usually made of Al. They are above the local interconnect level. Global interconnects are thick, long, and widely spaced. They often travel over large distances, between different devices and different parts of the circuit, and therefore are always metals with lower resistivities.
Desirable/Expected VLSI Interconnect
Ideally we assume, wire only connects functional elements and does not affect design performance. Voltage changes at one end and appears at its other end without any delay, i.e. wire is an equal potential region.
Materials properties that are desirable in a metal interconnect material are :
i. Low electrical resistivity
ii. Low capacitance i.e. low dielectric constant.
iii. Low capacitance i.e. low dielectric constant (for low RC delay, cross talk, power loss)
iv. High electro-migration resistance.
v. Ease of deposition of thin films of the material.
vi. Ability to withstand the chemicals and high temperatures required in the fabrication process.
vii. Stable contact structures.
viii. Adherence to insulating films (SiO2 )
ix. Low internal stress, surface roughness
x. Easily etched using plasma processes
xi. Compatibility with all other semiconductor processes
xii. Low cost
Real/Fabricated VLSI Interconnects
Now let's try to understand how fabricated interconnects behave in real world. Interconnects have a resistance, capacitance, and inductance per unit length.
Wiring of IC forms a complex geometry that introduces:
i. Capacitive Parasitics,
ii. Resistive Parasitics
iii. Inductive Parasitics.
Parasitics have impact on circuit behavior, such as :
i. increases propagation delay causing a drop in performance.
ii. impact on the energy dissipation and the power distribution.
iii. Introduces extra noise resulting in the reliability of the circuit.
Modeling of the wire capacitance(s) is a not a trivial task. It require physical understanding of the device structure electrical understanding of the circuit and mathematical understanding of models used to describe capacitance. There are two types of capacitance occurring:
1. Parallel plate Capacitance ; 2. Fringe Capacitance.
Capacitance of a wire is a function of shape, distance to surrounding wires and substrate. The resistance of a wire is proportional to its length L and inversely proportional to its cross- section A. Inductance in interconnect is represented by voltage drop due to rate of change of current with time.
Parasitic Extraction :
Parasitic extraction is to calculate the parasitics of wires and create an analog model of the circuit. Extracted parasitics are included in timing, power analysis to get more realistic result. Standard Parasitic Exchange Format (SPEF) is an IEEE standard for representing parasitic data of wires in a chip in ASCII format.
Interconnect Parasitics in VLSI :
1. Resistance :
The resistance of a wire is :
Where L= length, A= cross section of the wire, H= Height
and W= Width of the wire,
= resistivity of the metal2. Inductance :
The inductance of a section of a circuit states that a changing current passing through an inductor generates a voltage drop.
An important source of parasitic inductance is due to bonding wires and chip packages.
3. Capacitance :
1. Parallel Plate Capacitance :
where W and L are respectively the width and length of the wire, and tdi and εdi represent the thickness of the dielectric layer and its permittivity.
2. Fringe/Fringing Capacitance :
The capacitance between the side-walls of the wires and the substrate. W,L are respectively the width,length of wire.
3. Total wire Capacitance :
Back End Of Line(BEOL)
The Back-End-of-Line (BEOL) is the portion of IC fabrication where the wiring is done through Metalization/Vias including Dielectric separators among various metal layers.
BEOL steps are like :
1. Silicidation of Poly-Silicon and Source/Drain Diffusion.
2. Then adding a Pre-Metal-Dielectric(PMD) & CMP processing it.
3. Make holes in PMD & create contact through It.
4. Add metal layer 1.
5. Then add dielectric layer a.k.a Inter-Metal Dielectric (IMD).
6. Through CVD make vias through IMD to connect lower and higher metal layer .
7. Carry on last three steps until all the metal layers as per the tech node are done.
8. Add final passivation layer to protect the chip.
BEOL Corners : C Worst, C Best, Cc Worst, RC Best, Rc Worst.
Resistance & Reliability :
Electromigration:
A chip may go above 100 Degree Celsius during practical operation. High frequency power loss & consequent heat dissipation contributes in increased temperature. Rise in temperature enhances solid-state metal ion diffusion. Electro-migration is caused by scattering of the moving electrons with the ions, i.e., by momentum transfer between electrons and ions in metal interconnects. This ion-electron interaction is sometimes referred to as "electron wind.” This causes the wire to break or to short circuit to another wire. Such situation void in interconnects can leads to open circuit i.e chip failure. EM is one of the most menacing and persistent threat to interconnect reliability.
Ohmic Voltage Drop:
Current flowing through a real wire results in an ohmic voltage drop that degrades the signal levels. The affected value of the voltage reduces noise margins and changes the logic levels as a function of the distance from the supply terminals. IR drops on the supply network also impact the performance of the system. A small drop in the supply voltage may cause a significant increase in delay.
RC Delay :
Signal doesn’t travel instantaneously in wires and the delay of a wire grows quadratically with its length. The signal delay of long wires is dominated by the RC effect. This is becoming even bigger problem in modern technologies. This leads to a siuation that take multiple clock cycles to get a signal from one side of a chip to its opposite end.
Capacitance & Reliability :
Capacitive Coupling:
In real world of ICs, each wire is coupled to both grounded substrate and also to the neighboring wires on the same layer and on adjacent layers. Some capacitive components connect to other wires with dynamically varying voltage levels. Such variable/floating capacitors causes cross-talk and a negative effect to the circuit. Delay in the signal transmission through wire is proportional to the capacitance charged. More capacitance means more dynamic power. Coupling capacitance is an increasing source of noise and makes delay estimation hard.
Methods to Reduce Interconnect Capacitance :
i. Use of low k dielectric which reduces permittivity and hence the capacitance.
ii. Increase the spacing between the wires (Not always possible).
iii. Separate the two signals with a power or ground line (acting as shield).
iv. Use minimum wire width wherever possible. (Increase resistance)
Crosstalk :
It occurs due to unwanted coupling from a neighboring signal wire to a network node. The resulting disturbance acts as a noise source. Capacitive cross talk is the dominant effect at current switching speeds. The potential impact of capacitive crosstalk is influenced by the impedance of the line under examination. The design functionality and its performance can be limited by noise. The noise impact can limit the frequency of operation of the design and it can also cause functional failures. Cross talk may lead to setup or hold violation.
Propagation Delay :
Capacitive cross talk may result in a data-dependent variation of the propagation delay. Coupling capacitance is a large fraction of the overall capacitance in the dense wire structures of advanced technology nodes. This increase in capacitance is substantial, and has a major impact on the propagation delay of the circuit.
Inductance and Reliability
L(di/dt) Voltage Drop :
During each switching action, a transient current is sourced from or sunk into the supply rails to charge/discharge) the circuit capacitances. Both Vdd and Vss connections are routed to the external supplies through bonding wires and package pins and possess a non ignorable series inductance. Change in the transient current creates leads to large current surges.
Transmission Line Effects:
When an interconnect becomes sufficiently long or when the circuits become sufficiently fast, the inductance of the wire starts to dominate the delay behavior and transmission line effects become significant.
Impact of Scaling :
Wires are subdivided into short and long wires. Short wires are typically used for local communication between gates. Long wires are used for long range communication at the different corners of of the IC.
Watch the video lecture here :
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