In this article we willl discuss about delay models in interconnects. I/P to O/P delay in IC has 2 components : gate & interconnect delay
Gate Delay :
The figure shows a Gate /Propagation delay of NOT gate. O/P changes after a delay of “DELTA” with change in I/P. Gate delay is not equal for high to low and low to high transition.
Wire Delay :
Interconnects or wires connecting active devices add delay while carrying signal. This is wire delay. Wire delay is also known as transport/ flight delay. Wire delay become dominating with higher operating frequency i.e., lower device dimension.
Delay Models :
RC Network and Gate Delay Modeling :
RC circuits are frequently used to model the timing characteristics of ICs. When one logic gate drives another gate, the input ckt. of the second gate can be modeled as an RC load. The propagation delay through the first gate is calculated by assuming Vin as ideal square wave and the RC load. Gate delay is inversely proportion to the switching speed of the gate.
RC Network and Wire Delay Modeling :
A wire can is modeled as many cascaded sections of simple RC circuits. When a square wave is applied to one end of the bus, it takes time to propagate. This delay time due to the wire can be calculated based on the values of R and C in each section and the number of sections used to model the wire. The longer the wire, the more sections are needed for accurate model.
Wire load Model (WLM) : WLM is used to estimate delay based on area and fanout. Semiconductor vendors develop wire load models. Used in pre layout design cycle.
Lumped C Model :
Ckt. parasitics of a wire are distributed along its length and are not lumped into a single position.
Lumped Model is considered in a circuit where :
i. single parasitic component is dominant
ii. interaction between the components is small iii. one aspect of the circuit behavior is considered
Effects of the parasitic can be described by an ordinary differential equation. If parasitic R is negligible and ckt. is operating in low to medium range, only capacitive component is considered. Distributed capacitance lumped into a single capacitor. That is Lumped C Model. Suited well for older tech node where wires were wide. High cross sectional area A ( H X W) means less R.
In this model wire is equi-potential region & wire does not introduce any delay. Impact on performance is introduced by the loading effect of the capacitor on the driving gate. This capacitive lumped model is simple and effective. Model of choice for the analysis of most interconnect wires in older tech node.
Lumped RC Model:
Lumped RC model is used when : (i) wire length L > few mm, (ii) resistive component is considerable. With scaling wire cross section is reduced & R become considerable. Lumped C model is inadequate.
Interconnect is modeled with resistive capacitive/RC model. Multiple approaches are there depending on complexity and operating condition of the ckt and verified with accuracy of the result. In lumped RC model the total resistance of each wire segment is lumped into one single R and global capacitive is combined the into single capacitor C.This model is pessimistic and inaccurate for long interconnect wires, which are more accurately represented by a distributed RC model.
RC Networks :
Studying lumped RC network is important as, the distributed RC model is complex and no closed form solutions exist. The behavior of the distributed RC line can be, adequately modeled by a simple RC network. A common practice in the study of the transient behavior of complex transistor-wire networks is to reduce the circuit to an RC network. Analysing such a network effectively and to predict its first-order response is important for designers. Two popular Network : Tree Network & RC Chain/Ladder Network
Pi and T Models:
The distributed RC delay can be modeled by breaking up a wire into one or more segments and using a lumped model for each segment. Popular lumped models are Pi and T model (named for their shapes). R and C depend on the length of the segment. Pi and T model, are both good models. Although Pi model is slightly more convenient because of fewer circuit nodes. Most circuit simulators have built-in distributed rc-models of high accuracy.
Elmore Delay Model :
Derived originally in the 40s for circuits applications and applied in 80s for RC trees. Elmore defined delay through linear network as the first moment of the network impulse response. The Elmore delay formulas are immensely useful and simple model. Layout peoples use in algorithms( Single time constant). More accurate compared to simple length-based schemes. Although later verification required (not super accurate! ) with higher order models that incorporate more than one time constant.
Simple RC model provides general approximation of timing behavior of digital integrated circuits Elmore delay model is used in order to improve accuracy of RC model. Here, the RC segments made up of series resistance Rn and a capacitance Cn are created. Think of current like real water, flowing in tree. From any component of tree,looking at the source, it’s UPSTREAM & look toward leaves, its DOWNSTREAM.
RC Tree Network with Elmore Delay:
Wire branching into many destination modeled as an RC tree. Its a tree of resisters. Root of the tree is at the source node S where input signal is applied. There is no loop. At the branch end output is measured. Each intermediate node is grounded with a capacitor. There exists a unique resistive path between the source nodes and any node i of the network. The total resistance along this path is called the path resistance Rii.
The path resistance between the source nodes and node 4 is expressed as , R44 = R1+R3+R4.
The path resistance of the shared path can be expressed as resistance Rik = effective resistance between the input and node k in common with the path between the input and node I :
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So using above formula Ri4 = R1+R3 ; Ri2 = R1. The Elmore delay from the source to node i of an RC tree is given by :
N = number of nodes in the tree, Ck = capacitor on node k , Rki = shared resistance between node k & I.
Elmore delay for network = Tdi = R1C1+R1C2+ (R1+R3)C3+ (R1+R3)C4 + (R1+R3+Ri)Ci
RC Chain with Elmore Delay Model :
A special case of the RC tree network : non- branched RC chain or ladder. In digital circuits similar structure is found. Represents an approx model of a resistive-capacitive wire.
The delay component of :
Node 1 = C1R1 ( R1 is the total resistance between the node 1 and the source)
Node 2 = C2(R1+ R2) ( R1+R2 is the total resistance between the node 2 & source )
Delay = Sum (Cap i * Resistance from Source to Cap i)
= R1C1 + (R1 + R2) C2 +...+ (R1 + R2 + R3+...+Ri) Ci
This gives the right answer for all values of C and R unless R or C have value equal to 0. t is the only equation that is correct in all the limits.
Distributed RC line Model :
A distributed rc line model is a more appropriate model. r and c stand for the resistance and capacitance per unit length. The voltage at node i of this network can be determined by solving the following set of partial differential equations:
by reducing asymptotically to 0 , we get ,
where V is the voltage at a particular point in the wire, and x is the distance between this point and the signal source.
These equations are difficult to use for ordinary circuit analysis. The distributed rc line can be approximated by a lumped RC ladder network,which can be easily used in computer-aided analysis.
Transmission Line Model :
The inductance is distributed over the wire, like R and C. A distributed rlc model of a wire, known as the transmission line model, becomes the most accurate approximation of the actual behavior. In Transmission Line Model , a signal propagates in interconnection medium as a wave (In distributed rc model, where the signal diffuses from the source to the destination governed by the diffusion equation) . In the wave mode, a signal propagates by alternatively transferring energy from the electric to the magnetic fields, or equivalently from the capacitive to the inductive modes.
Assuming that the leakage conductance g equals 0, which is true for most insulating materials, and eliminating the current i yields the wave propagation equation:
where r, c, and l are the resistance, capacitance and inductance per unit length respectively.
Consider the point x along the transmission line of figure as shown above at time t. The following set of equations holds:
Lossless Transmission Line :
For the lossless Transmission line, r= 0 and the previous equation simplifies to the ideal wave equation:
Step input propagates with speed ν
Values of both l and c depend on the geometric shape of the wire, their product is a constant and is only a function of the surrounding media. The propagation delay per unit wire length (tp ) of a transmission line is the inverse of the speed:
Watch the video lecture here :
