With gradual down-scaling of MOS devices, parasitic effects specially inductive parasitic effect becoming more and more significant. In this article we will discuss about on chip inductance.
How On-Chip Inductance Become Significant?
On-Chip Inductance effects have become increasingly significant because:
1) Some global signal and clock wires have large widths and thicknesses at the top level of the metal to minimize delays. This decreases the resistance of the wires, making their inductive impedance comparable to the resistive part. There is more to impedance than resistance: Z = R + jωL . When ωL is comparable to R, inductive effects must be considered.
3) Signal transition times become much shorter (comparable to the signal time of flight) and devices become faster.
4) With the increase of chip size, it is fairly typical that many wire are long and run in parallel, which increases the inductive Cross talk and delay.
5) With the push of performance, some low-resistivity metals,e.g. Cu wires, have been explored to replace Al in order to minimize wire RC delays. This could make the wire inductive reactance larger than the resistance.
Interconnect Model Mapping with Tech. Nodes:
Loop Inductance: Loop inductance is defined as the induced magnetic flux in the loop by the unit current in other loop,
where, ψ ij represents the magnetic flux in loop i
due to a current I j in loop j.
Partial Inductance:
Problem with loop inductance:
Calculation of loop inductance require knowledge of return paths. Its really difficult to determine return path for on-chip interconnects explicitly since there in no ground plane. Almost every wires couples to many wires, and there are multiple return paths.
Properties of Partial Inductance:
Partial self and mutual inductance are based on geometry only. They may be solved by using a 2D/3D field solver. The return path or the current loop may be determined through SPICE simulations. The partial self and mutual inductance may be frequency and proximity dependent.
Transmission Line Model :
The inductance is distributed over the wire, like R and C. A transmission line model, becomes the most accurate approximation of the actual behavior. In TL Model , a signal propagates in interconnection medium as a wave:
For the lossless Transmission line, r= 0 and the equation becomes:
Dependence of Impedance on Frequency:
In a circuit with multiple current paths the distribution of the current flow is frequency dependent
– at low frequency current path is determined by the resistance of the paths
– at high frequency current path is determined by the inductance of the paths
This effect is the primary source of inductance variation with frequency in integrated circuits.
Impact of On-Chip Inductance:
Any current passing through a conductor creates a magnetic field. This magnetic field then induces a parasitic current either on the same metal (i.e self-inductance), or on another metal crossing the magnetic field (i.e., mutual inductance).If we focus on resistance and inductance, we can express interconnect impedance as: Z= R+jwL
1. Skin Effect : A high frequency phenomenon. As frequency increases, the current tends to flow closer to the conductor surface or skin, between the outer surface and a level called the skin depth. It is defined as the depth where the current density is just 1/e (about 37%) of the value at the surface. Skin effects increase the resistance parasitics of a conductor at at high frequency. They also lead to a frequency-dependent value for the effective inductance and resistance seen by the current. Such effects must be included in the parasitic extraction to achieve accurate results.
Proximity Effect : When two or more conductors carrying a.c are close to each other, then distribution of current in each conductor is affected due to the varying magnetic field of each other. The varying magnetic field produced by a.c. induces eddy currents in the adjacent conductors. When the nearby conductors carrying current in the same direction, the current is concentrated at the farthest side of the conductors. When the nearby conductors are carrying current in opposite direction to each other, the current is concentrated at the nearest parts of the conductors. This effect is called as Proximity effect.
The proximity effect also increases with increase in the frequency. Effective resistance of the conductor is increased due to the proximity effect.
Difficulties with Inductance:
It Depends on Frequency. Inductance of a Wire Requires Knowledge of Return Path(s). The Vss or Vdd closes loop for each piece of interconnection. The return path is decided by signal pattern and interconnect geometry for a large range. Often return path is not easily identified, particularly at layout stage as it is not necessarily through the silicon substrate. Silicon substrate cannot be considered as a ground plane as the resistivity of the doped substrate layer is very high compared to metal and the substrate is too far away from the high-speed buses or clock wires. Mutual Couplings Between Wires Decrease Very Slowly. Magnetic fields die out at a far distance as compared to the electric fields. Considering near neighbors which is enough for capacitance is not enough for inductance. Reason of concern for high frequency designs. Inductance is not scalable. Inductance results in many high frequency poles and zeros, making Reduced Order Model Approximation difficult.
Minimizing On-Chip Inductance:
1. Dedicated Ground Wires : Increase the mutual inductance by making the signal wire and its return path to be as close as possible. Decrease the self Inductance by increasing the width of the return path, or by adding one or more ground wire in between signal wires.
2. Differential Signaling : This method has high signal-to-noise ratio due to the common mode noise rejection, however, requires double the number of signal paths as compared to single-ended transmission networks. The transmitter
at the near end of the network converts the single-ended signal into an opposite polarity differential signal, while the receiver at the far end of the transmission lines converts the differential signal into a single ended form.
3. Splitting Wires : Splitting a wide wire into several N parallel wires of about two skin depths width each may reduce the total reactance by a factor of N.
4. Continuous Power / Ground Planes : When signals travel a long distance for current return without planes nearby that causes inductive coupling. A continuous power/ground plane greatly reduces the coupling.
5. Buffer Insertion : With inserted buffers, inductive coupling decrease slightly faster than a linear rate. Each segment becomes more an RC line than an RLC line. Because L per segment scales down at a rate faster than the R,C.
6. Shielding : Shielding techniques are widely used to reduce capacitive and inductive coupling. Isolates an aggressor/noisy line from sensitive neighboring lines. Increases the noise tolerance of a sensitive line. The voltage of the shield lines typically does not switch. By inserting a shield line between signals lines, changes in the effective interconnect capacitance is significantly reduced, resulting in less delay uncertainty. Inductive coupling and self inductance can also be reduced by inserting shield lines, since the shield line provides a nearby current return path.
7. Termination :The behavior of the transmission line is strongly influenced by the termination of the line. The termination determines how much of the wave is reflected upon arrival at the wire end. This is expressed by the reflection coefficient ρ that determines the relationship between the voltages and currents of the incident and reflected wave forms.
Z0 = characteristic impedance
i) If R= Z0 , ρ=0 , the termination appears as an infinite extension of the line, and no waveform is reflected.
ii) If R = ∞ , ρ = 1. The total voltage waveform after reflection is twice the incident one.
iii) If R = 0 , ρ = -1. The total voltage waveform after reflection equals zero.
Significance of Termination :
To reduce the coupling noise at the inputs of victim receivers diff. termination methods are used:
1) Series RC Termination,
2) Series R Shunt C Termination,
3) Series R Termination,
4) Diode Termination
The amplitude of the ringing depends on the degree of mismatch at either end of the line while the frequency depends on the electrical length of the line.
Modeling of Interconnect at High Frequencies
At high frequencies circuit dimensions become comparable to signal wavelengths and it is not always possible to identify discrete parasitic element. There are some models used to extract parasitics at high frequencies:
1)Field Solver
2)Finite Element Method
3)Moment Method
4)Boundary Element Method (BEM)
5)Finite Difference Time Domain (FDTD) Method
6)Transmission Line Matrix (TLM) Method)
7)Partial-Element Equivalent Circuit (PEEC) Method
Watch the video lecture here :
