In this article we will discuss about Signal Integrity and Cross-talk. Once completed you will be able to answer below questions:
1. What is signal integrity and what are common signal integrity issues?
2. What is cross talk and how it impact signal integrity?
3. Different types of glitch : Rise glitch, Fall glitch, Overshoot Glitch, undershoot Glitch.
4. Different types of cross talk delays : Positive and Negative delay.
5. Impact of delay on set up and hold timing
6. How to minimize impact of cross talk?
Signal Integrity in Physical Design:
In digital electronics a stream of binary data is transmitted as signal and it represented as voltage (or current) waveform. All signals are subject to noise, distortion and loss. Signal Integrity is the measure of quality of a signal as it travels from one point to another point. Signal integrity is crucial as it ensures whether the data transmission is accurate, reliable, and immune to unwanted effects such as noise, distortion, and reflections. If the signal faces above mentioned unwanted continuously, it can lead to erroneous data transmission.
The signal integrity mainly deals with : 1. timing and 2. quality of the signal. Signal integrity is both an interconnect level problem, as well as a systems-level problem. Any design have some signal integrity problem and they generally do not interfere with the functionality of the system by creating excessive, until the system deals with high frequency signals.
Common Signal Integrity Issues in PD :
In a digital system SI analysis are done in three levels :
1) logic level , 2) circuit level , 3) EM field level.
In logic level analysis Signal Integrity issues can be easily identified. Circuit level Signal Integrity analysis is based on interconnect modeling. Here we try to model a piece of interconnect including resistive, capacitive and inductive effect. At Electro-Magnetic level, most of the signal integrity issues are reflection, cross-talk, ground bounce etc. Circuit level analysis obtain a good SI solutions at low frequency whereas for state-of-art ICs with small dimension and high operating frequency EM level analysis is more accurate to describe the effects. SPICE tools are used to check SI in nodal analysis and they solve voltage and current in the RLC circuit.
Here are the major issues concerning signal integrity:
1. Cross-talk Delay
2. Cross-talk Noise
3. Ringing & Ground bounce
4. IR (voltage) drop in power lines
5. Electro - migration
6. Manufacturing-related issues that if not addressed can lead to chip failure (Antenna Effect)
Cross-Talk :
Cross-talk is the undesirable electrical interaction between two or more adjacent nets due to capacitive coupling. Switching of the signal in one net (aggressor) can interfere neighboring net (victim)due to coupling capacitance this is called cross talk. Aggressor is a net which creates impact on the other net. Victim is a net which is impacted by aggressor.
Cross-talk has two effects : Cross-talk Noise & Cross-talk Delay
Cross-talk Noise/Cross-talk Glitch:
-Signal transition in aggressor causes a noise bump or glitch on victim net. This in known as cross-talk noise.
-Cross-talk noise/glitch/bump occurs when aggressor net switches and the victim nets remain in a steady state.
Cross-talk Delay/Cross-talk Delta Delay:
-Signal transition in aggressor create delay in the output transition of victim. This is known as cross-talk delay.
-Cross-talk delay occurs when both aggressor and victim nets switch together.
Classification : Rise & Fall Glitch
Lets now discuss about Rise and Fall Glitch.
Rise Glitch : Victim net is at a steady low, aggressor net is switching low to high.
1. G1 I/P→ 1to 0 and node A , 0→ 1.
2. Node A, 0 →1 , Cm starts to get charged.
3. O/P of G3 and Node V at 0.
4. Leakage current through Cm create a rise in voltage glitch at V.
Fall Glitch : Victim net is at a steady high, aggressor net is switching high to low.
1. G1 I/P→ 0 to 1 and node A , 1→ 0.
2. O/P of G3 and Node V at 1.
3. Node A switches from 1to 0 and Nove V at 1.
4. Leakage current Cm flows from V to A and
create fall in potential at V.
Classification :Over & Under Shoot Glitch
Over Shoot Glitch : Victim net voltage is at steady high and aggressor net is switching from
low to high, induces overshoot glitch by taking the victim net voltage above its steady high.
What Impacts Glitch?
Not all glitches are considered unsafe for circuit operation. Safe/Unsafe decided by glitch height.
Glitch Height : Magnitude or height of the glitch is determined by few factors. Such as:
1. Value of Coupling capacitance :
Magnitude of glitch would be higher if the coupling capacitance value is higher.
2. Slew of the aggressor net:
If the output drive strength of the cell that is driving the aggressor net is high, slew of the aggressor net is faster. The faster slew of the aggressor net results in high magnitude of glitch.
3. Drive strength of aggressor and victim net:
If driving strength of aggressor net is high the magnitude of the glitch will be higher, whereas if driving strength of the victim net is higher it is not easy to influence it.
4. Grounded Capacitance :
If victim net grounded capacitance is small then the magnitude of glitch will be large.
Multiple Aggressor :
When multiple aggressor are present and they switch concurrently the impact on victim net is get added.Concurrent switching is an ideal case. In reality more than one aggressor net can switch together or their switching action can share same time window. So the impact on victim net depends on the contribution of each aggressor node on that victim net for a time window.
Range of Safe & Unsafe Glitch :
- Safe Glitch : Has no effect on logic state of victim net.
- Glitch height < Noise Margin Low (NML), a safe glitch.
- Glitch height > Noise Margin High (NMH), a unsafe glitch.
- NML < Glitch Height < NMH , an unpredictable case.
- Noise margin is a parameter that determines the allowable
noise voltage on the I/P without affecting O/P.
- Noise margin/immunity expressed in terms of NML, NMH.
- NMl = Vil – Vol (difference in magnitude between the max.
LOW output voltage of the driving gate and the max. input
LOW voltage recognized by the driven gate).
- NMh = Voh - Vih(difference in magnitude between the min.
HIGH output voltage of the driving gate and the min. input
HIGH voltage recognized by the receiving gate)
Cross-talk Delay Basics:
Crosstalk delay occurs when both aggressor and victim net switching. It may leads upto setup and hold timing violation. Crosstalk delay increase or decrease the delay of a cell depending upon the switching direction of aggressor and victim nets. There are two types of cross-talk delay: Negative Crosstalk Delay & Positive Crosstalk Delay
Negative Cross-talk Delay :
Aggressor and victim nets switch in the same direction :
2) If aggressor has higher driving strength, transition will happen faster.
3)A potential difference from node A to V will be developed.
4) Node A will try to pull up the victim node.
6) Victim net will reach from 0 to 1 earlier and transition time will decrease.
7)Cross-talk will be decrease the delay by Δ and the new delay will be (D – Δ).
Positive Cross-talk Delay :
Aggressor and victim nets switch in the opposite direction :
1) Aggressor net and node A switches from 0→ 1.
2) Victim net or node V switches from 1→ 0.
3) There will be a potential difference from node A to V.
4) Node A will try to pull up node V.
5) There will be a bump in victim net waveform.
6) Transition of the victim node will have a bump.
7) Victim net will take longer time to reach from 1 to 0.
8) Transition time will increase.
9)Cross-talk will be increase the delay by Δ and the new delay will be (D + Δ).
Effects of Cross-talk Delay:
1. Effect on clock tree: Cross talk can unbalance a balanced clock tree. Cross-talk delay can change the latency of balanced path and the clock tree become unbalanced.
2. Effect on Setup timing:
For setup timing data should reach the capture flop before the required time of capture flop. Setup time violation occurs due to increase of delay in data path/launch clock path, decrease in delay on the capture clock path
3. Effect on Hold timing:
For hold timing data must be stable for minimum amount of time after the clock's active edge. Hold time violation occurs due to decrease of delay in data path, launch clock
and increase of delay in the capture clock.
Cross-talk & RT Level Estimation :
Each design stage has its own models for cross-talk.
Trade-offs exist between the accuracy and complexity
of these different models. The cost involved in detecting errors and correcting them increases by a factor of 10 between each abstraction level as we move top-down in the ASIC design flow. Detecting cross-talk sensitivity at the gate-level is 10 times more expensive than detecting it at the RT-level. Some low level parameters have direct impact on cross-talknoise problem and those cannot be accurately determined at higher abstraction levels. Such parameters are :
1. The positions of the modules, relative to one another(can be determined after floor-planning )
2. The route of each wire (can be determined after floor planning)
3. The aggressors of a given wire in both the horizontal and the vertical planes (can be determined after floor planning)
Thus, high-level cross-talk estimation in includes mathematical and statistical process.
Mitigation Methods of Cross Talk:
1. Increasing the space between aggressor and victim net:
If the distance between aggressor and victim nets is increased, the mutual inductance between them will decrease.
2. Insertion of Shielding Net :
Inserting a net which is connected to Vss/Vdd between critical aggressor and victim net is a method. This new net in between works as shield, and this process is known as shielding. Process of shielding stops direct coupling between aggressor and victim net and since the shielding net remain at constant potential chances of cross-talk is completely waived off.
3. Upgrading drive strength of victim cell :
If we upgrade the driving strength of victim cell, it will not be easy to change its logic state.
4. Downgrading drive strength of aggressor cell :
If we downgrade the driving strength of aggressor cell, its impact on victim cell will decrease.
5. Buffer insertion:
Insertion of buffer effectively boost the victim net strength.
6. Guard Ring :
Guard ring in the substrate use to shield the analog circuitry from digital noise.
Find the video lecture here:
