Engineering change order (ECO) is a bug fix method on the actual chip design and/or in layout with minimal disturbance to the existing implementation. It helps in saving Turn Around Time(TAT) and already-spent optimization efforts and hours at various design stages. Due to continuous increase in the design complexity the metal mask ECOs have become inevitable. ECOs accommodate design specification changes for various reasons. These include rectification of functional errors. Also include non-functional design requirements such as timing and power. In present days EDA tool vendors provide inbuilt ECO solutions. In addition customized scripts can be there to improvement due to ECO’s high computational complexity and algorithm. It is also possible to include Engineering Change Orders (ECOs) even after the first tape out.
VLSI ASIC Design Flow & ECO:
The above diagram shows stages of VLSI design. Upto DFT/Sxcan-chain it is Front End and from Floor Planning the Back End starts. There are two types of ECO : one is done before mask generation and another is done after mask generation.
Pre-Mask ECO Flow
The Pre-Mask ECO flow can be divided into 6 main steps.
1. Describe an ECO specification.
2. Capture the specification.
3. Compare the ECO netlist with the design netlist.
4. Update the placement with ECO changes.
5. Perform the ECO routing.
6. Insert filler cells.
Post-Mask ECO Flow:
1. Post-mask ECO using conventional spare cells.
2. Describe and Capture the specification.
3. Compare the ECO netlist with the design netlist
4. Check the feasibility of the spare cells
5. Carry out Spare cell Mapping
6. Perform the incremental routing and fix the routing DRC.
7. Perform Formal Verification
Types Of ECO by Design Stage:
Types OF ECO Based On Analysis:
ECO Target Detection Through Analysis:
Various ECO Cells:
Generally, redundant standard cells, known as spare cells, are used to realize such type of ECOs. However, these cells suffer from a major drawback of having predefined functionality and location. As a result, their use becomes limited. To overcome this inflexibility, gate array type spare cells are used. As the gate array spare cell are configurable, it opens up new possibilities of doing big ECOs.
Spare Cells:
Spare cells are like most standard cells and have a fixed functionality. Appropriate combination of spare cells of various functionalities are chosen to ensure the desired functionality is available when an ECO modification exercised. Apart from these some of the standard cells may get converted into spare cells to meet ECO design changes. Spare cells which are tie-high and tie-low , contribute to leakage power. Tie-high and tie-low are necessary to avoid a direct connection between the power/ground nets and to avoid Electrostatic discharge (ESD) events. Unused spare cells block unusable area in the chip. Hence number of unused spare cells should be reduced.
Re-Configurable Cells :
As per the need these cells can be reconfigured into a desired logic function to perform the ECO modification. Unused Re-configurable Cells are by default reconfigured into decoupling capacitors (DECAP). This leads to a more efficient use of the available area and if the IR-drop becomes more significant, decoupling capacitors will address that. Another advantage of the use of re-configurable cells is that tie-high and tie-low cells are no longer needed and hence reduction of overall leakage power.
Metal-Configurable Gate-Array Cells:
Re-configurable cells lags in a situation when cells with an higher complexity and/or different driving capabilities are required, multiple re-configurable base cells needs to be interconnected. This adds extra delay that induces timing degradation. Solution to this could be insertion of both re-configurable cells (for the more simple logic gates) and spare cells (for the most complex ones) together. Another solution for this is Metal-Configurable Gate-Array (GA) cells a.k.a GA Re-Configurable cells. They consist of an array of tiles in which each tile represents a basic re-configurable cell. If a more complex logic gate is desired, multiple adjacent tiles can be used.
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