Standard Cells : Building Block of ASIC
Standard cells are the building blocks of ASIC designs. We can understand this with a simple analogy shown in above figure of Lego blocks kids loves to play with. A chip is built with different types of IPS and majority of them are standard cell IPs.
Standard Cell : Introduction
Standard Cell Libraries are required by all tools used in the ASIC Design RTL-to- GDS flow. It contains primitive cells as well as complex cells too. Standard Cells are designed by Variation of Power-Performance-Area (PPA). For each cell a variety of drive strengths are present. Inverters and Buffers have much Larger drive strengths varieties than any outer cells. Cells contains balanced rise and fall delays. Cell with delay variation present to aid fixing of STA violations. Standard Cell heights(dimensions) are denoted by Track. Variation may be 7T , 11T etc. The distance between two consecutive tracks is called the Pitch.
IP Classification & Standard Cells:
IPs are broadly categorized into :
1. Foundation IPs, 2. Standard based IP, 3. Application Specific ICs
1. Foundation IP : Standard Cell Library, I/O, SRAM, DRAM, BRAM, eNVM, ARM Core comes under this category.
2. Standard based IP : USB, PHY, SATA, PCIe, SD/eMMC are included in this category.
3. Application Specific IP : MP3, MPEG, Video-Cam belong to this category.
What is Inside Standard Cell Library
A Standard Cell package contains :
1. Basic Logic Gates : these are basic AND , OR gates.
2. Half Adder/ Full Adder : Half and Full adder , we know their functions from our knowledge of basic digital electronics.
3. ECO Cells : These cells are used during Engineering Change Order of Back End.
4. Tie Cells : These cells are used to tie with positive or negative power supply.
6. AOI/OAI : AOI is known as AND-OR-Inverter whereas OAI is known as OR-AND-INVERT. These are two level logic functions. AOI logic functions constructed from the combination of one or more AND gates followed by a NOR gate. OAI logic functions constructed from the combination of one or more OR gates followed by a NAND gate.
7. Flip-flops : Variety of Flip-flops are there in Standard Cell Library.
8. Scan Flops : These are special types of Flip-Flops specially used for DFT.
9. Latches : Various types of latches are there.
10. Filler Cell : These specials cells are used in Back End part.
11. Clock : These are clock related cells important for sequential logic.
Other than this , Tap Cell, End Cap Cell, D cap Cell, Mux etc are part of standard cell library package.
These are most generalized cells present in standard cell library.
VLSI Design Flow
VLSI design flow is categorized into Front End and Back End part. Now we will discuss about standard cells used in Front and Back End.
Standard Cell : Fornt-End Views
In front end mostly RTL views, specifically Verilog, Vhdl, System Verilog, DB, SDB, SLDB, UPF,CPF,OA etc.
Standard Cell : Back-End Views
In back end there are layout related views like Mapping Files, NDM Files, GDSII Files, LEF, DEF, DB, OASIS, CIF, Abstract View etc.
Variation : Track/ VT / Drive Strength
Now we will discuss about variation in standard cells depending on various parameters. Here we will discuss about Track, VT and Drive Strength.
7T-8T Std-Cells are used for area efficiency. 9T-10T Std-Cells are used for reasonable area-performance trade-off. 11T-12T Std-Cells used for performance while have high leakage of it is taken into consideration.
Multiple Drive Strength : Each cell will have various sized output stages. Larger output stage, better at driving fan-outs or loads. Smaller drive strength, less area, leakage, input cap.
Multiple Threshold (MT-CMOS) Cells : A single additional mask can provide more or less doping in a transistor channel, shifting the threshold voltage.
Most libraries provide equivalent cells with three VTs, i.e, LVT, HVT, UHVT and more variations, to tradeoff speed vs. leakage. All threshold varieties have same footprint and therefore can be swapped without any placement/routing iterations.
Summary:
Standard Cell Library is a collection of basic as well as Advanced Cells. Standard Cells will contain consolidated Timing Library (.lib) for all the cells. One particular cell will have multiple views and variations based on parameters like Track/VT/Drive Strength. Volume wise Standard Cells are the biggest IP collection under Foundation IPs. Without the Standard Cell Library the Digital VLSI SOC Design is impossible !
Watch the video lecture here:
Courtesy : Image by www.pngegg.com
