What is IR Drop in VLSI ?

For continuous downsizing of technology nodes the chip operating frequency is continuously increasing at which the timing-related defects, coming out of high speed test, are in high proportion. DFT techniques may cause the test vectors to contain non-functional states which result in higher switching activities compared to the functional mode of operation. Excessive switching activity causes higher power dissipation which in turn may cause IR Drop hot spots that could cause damage the circuit. Due to the higher IR drops which increase signal propagation delays during test causing yield loss.

Power Delivery Network : Significance

The Power Grid simulation in ASIC causes Power Delivery Network (PDN) to turn on all the leaf cells inside any VLSI circuit. IR Drop is the excess voltage drop caused by the Parasitic RLC of metal routes from the PDN happening even before the desired voltage can reach the target power pins of the Standard Cells, IPs-Block or Macro-Blocks. Power buses carry large DC currents causing large IR Drop which in turn gradually reduces Vdd towards the center of a chip when the power supply is driven by pads around the perimeter.

IR Drop and Ground Bounce:

The total IR drop is further divided into has a resistive and an inductive sub-components. The resistive voltage drop (“on-chip IR drop”) is mostly due to the voltage drop due to on-chip metal/via interconnect resistance. The inductive voltage drop ("di/dt noise") is mostly caused by the pin-package  inductance. The “di/dt” often referred to as  Simultaneous Switching Noise (SSN) [ a.k.a Ground Bounce ]which is caused by rapid changes in the current passing through the parasitic inductors in the power network.

IR-Drop in IP/Analog & ASIC Design:

Resistance of Metal Strip & KCL/KVL

Simple Circuit Diagram & Parasitics

IR Drop Classification

Static IR Drop

IR-Dropstatic = Iavg x Rwire-segment [Iavg are all factors of leakage currents ] Static IR drop is an average voltage drop for the design. Hence is stimulus vector dependent. Vectors are taken from (1) The switching probabilities of each cell (2) applied switching probability of sequential cells. The Average current depends totally on the time period of the clock. Static IR drop is dependent on the RC of the power grid connecting the power supply to the respective standard cells.Static IR Drop. The PDN is reduced to a resistive network and the voltage drop across this resistive network is calculated  based on a given current source. Loads are assumed to be driven by the PDN. The Static IR Drop is performed around all production RC and PVT Corners Combined . Gate-channel leakage current is the major reason for the static IR drop. Static IR drop was good for signoff analysis in older technology nodes where sufficient natural decoupling capacitance from the power network and non-switching logic were available. Sometimes switching factors can derived from the functional waveforms from SAIF/VCD files.

Dynamic IR Drop: 

Unlike static method, in reality no two cells inside chip receive the same supply voltage due to placement , nearby cell activity and dynamic nature of its operation. Thus each Standard Cell have its unique dynamic voltage signature for its power/ground pin. 

Cycle to cycle dynamic voltage variation depends on : 

1. Overall change in peak current which causes RLC oscillation/noise in board/IC- packaging.

2. Change in toggle rate of local cells, which could result in temporary depletion of charge and high frequency noise drop.

Here the PDN is modeled as a network of impedance and a time-domain/transient analysis is done.  Here the IR drop is caused by high speed switching of transistors inside logic cells. Peak current demand shoots off when a large number of circuitry switches at the same time. Hence Dynamic IR Drop is less dependent on the a clock period and can't be modeled by pure traditional Static Timing Analysis. Preventive IR Drop analysis and investigative analysis is test pattern specific.

IR Drop & Timing Analysis

Undetected IR Drop can be compensated by means of increasing the supply voltage. Extreme cases it could also lead to Timing Analysis failure whose root-cause is higher voltage drop above specified Threshold/Margin. Dynamic IR Drop neither can be detected nor modeled by Static Timing Analysis. IR Drop can cause setup violations on the data path signals. IR Drop can cause hold time violations on the clock tree network. Delay of a cell depends on the voltage difference [𝑉dd(t) − 𝑉ss(𝑡)]. This delay increases with increase of Standard Cell threshold voltage while we vary in manner ULVT, LVT, STV, HVT & UHTV.

IR Drop with Multiple Power Domains

Power distribution among multiple power domain (PD) in a single chip is significant in floor-planning and placement phases. The PnR tool synthesizes the power distribution networks based on the power budget specifications for each domain while keeping Power network constraints under consideration. IR drop map is used to analyze the power network. If the Analyzed Maximum IR drop is not  acceptable then re-constraint and re-synthesize are done. After the IR drop becomes acceptable, the new Floor-Plan is created with added P/G pads. 

Thermal Hot Spot by IR Drop :

The heat produced in a Chip is proportional to its dissipated power. An excessive power dissipation during operation will increase the circuit temperature well beyond safe zone causing permanent physical damage. Such zones are predicted by Dynamic IR Drop Analysis are referred to as Hot-Spots. Thermal gradients and hot spots are due to various different functional blocks with different power dissipation over current or voltage stress for a long time of continuous operation.

IR Drop Mitigation:

High IR drop impact on clock tree network causing hold-time violation while IR drop on data path signal nets causes setup-time violations. To deal with such situation one may separate the standard cells , with high switching activity, apart so that the burden on a given bump to feed many standard cells can be mitigated. With padding clock cells technique, clock buffers/inverters and clock gate cells are given extra space as to keep out regions to avoid placement of standard cells and any excessive cell density around them. Decap insertion around cells within a dynamic IR hotspot region is another way of mitigation. High driving strength standard cells create dynamic IR drop issue. Cell padding is used for these cells or insert decap cells around it to mitigate IR Drop.

Summary:

Most of the times undetected Silicon IR drop may lead to appropriate voltage not reaching a transistor in CMOS. This can be compensated by increasing the supply voltage but may contribute to Timing Analysis failure for extreme cases. If the IR Drop exceeds a specified threshold typically (say, 10% of Vdd) the chip could become defective. IR Drop analysis is necessary for both at the block level and chip level to assimilate preventive design strategy. IR drops get to be a bigger problem as lower supply voltage are used in the lower technology node. IR drops in metal routes cause the wires to heat up. Oxide is a good heat insulator, so over time IR Drop may build up heat in the metal routes. This can degrade metal wire resistance and performance over time. When the wires get hotter, they become more resistive, causing more IR drops and more heat until the wire melts down! This is called thermal runaway. This may cause burn-out problem.

Watch the video lecture here :

Courtesy : Image by www.pngegg.com