In this article we will discuss about low power design. Once completed you will be able to answer below questions :
1. How many tyoes of power dissipation are there in CMOS VLSI design?
2. What approaches are taken in VLSI design to get rid of these power dissipation?
Low power design is the need of the hour. The rapid growth of smart watch industry, smart phone industry and wearable medical gadget industry has enforced that. An IC’s total power consumption comprises two types, static and dynamic. Static power typically comes from leakage current and dc current sources. Dynamic current consumption, which is frequency-dependent, often dominates total power. EDA tool vendors now offer low-power optimization tools & methodologies together to handle low power design.
Power Analysis of CMOS Circuits :
The power consumption of CMOS circuits consists of three components:
i. The dynamic power component.
ii. The short-circuit power component.
iii. The static power component, due to leakage.
Power can be estimated at a number of levels which include:
i. Circuit Level Power Estimation, using a circuit simulator such as SPICE
ii. Static Power Estimation does not use the input vectors, but may use the input statistics. Analogous to Static Timing Analysis.
iii. Logic-Level Power Estimation, often linked to Logic Simulation.
Analysis at the Register-Transfer Level. Fast and high capacity, but not as accurate. The power dissipation in circuit can be classified into three categories as described below.
Dynamic Power Dissipation:
Due to logic transitions causing logic gates to charge or discharge load capacitance.
Short-Circuit Power Dissipation:
In a CMOS logic P-Branch and N- Branch are momentarily shorted as logic gate changes state resulting in short circuit power dissipation.
Figure shows that the power is consumed because of the momentary current flow that occurs when both transistors conduct during a logic transition. This is Short-Circuit Current.
Static/Leakage Power Dissipation :
This is the power dissipation that occurs when the system is in standby mode or not powered. The sub-threshold region is regarded as an undesirable characteristic of MOS transistors that appeared as a dc leakage current in CMOS digital circuits.
There are many sources of leakage current in MOSFET. Diode leakages around transistors and n-wells, Sub-threshold Leakage, Gate Leakage, Tunnel Currents etc. Increasing 20 times for each new fabrication technology. Went from insignificant to a dominating factor.
Total Power Dissipation:
Total Power dissipated in a CMOS circuit is sum total of dynamic power,short circuit power and static or leakage power. Design for low-power implies the ability to reduce all three components of power consumption in CMOS circuits during the development of a low power electronic product. The general aim of the low-power designer is to reduce current consumption by minimizing the supply voltage, circuit complexity, clocking frequencies, dc current source values, and capacitance of switching nodes. Circuit functions that are continuously in operation are best implemented in analog circuitry.
Low Power Optimization:
From above discussion it is evident that total power consumption and power loss in VLSi design has multiple component. If we want to minimize the total power dissipation we must take care of each component.
Above diagram shows some methods we follow , like : clock gating, dynamic voltage scaling, power gating, retention flip flops, isolation cells, multi Vdd, Multi Vt, dynamic frequency scaling etc.
Clock Gating:
Clock network in a chip can consume 30-50% of the total Dynamic Power. In Clock Gating , Clock is temporarily turn off for the Switched-Off Power-Domain/block/blocks through a control signal. This control signal can be inserted by the RTL designer or inferred by the synthesis tool through Automated Clock Gating. The crucial part of Clock Gating depends on the choice of the right control signal for gating. Too much of clock gating can do harm than good as it may lead to increased dynamic power consumption. Hence judicial decision of clock gating is required.
Dynamic Voltage and Frequency Scaling :
The DVFS technique modulates the dynamic power based on the Variation Voltage and Frequency. This is generally used when workload is not CPU bound. Choice of the operating frequency generally back calculated from the work load and turn- around-time of the task. When the voltage is constant, then scaling down the frequency might not work.
Power Gating:
Summary :
An ASIC might contain several power optimization techniques such as the clock gating which is the most widely used technique to save dynamic power, Mutli-VT cells to reduce leakage power. As we going down in technology node, drastic power optimization methodologies like Dynamic Voltage Frequency Scaling (DVFS), Multiple-VDD and Power Gating are used.
Watch the video lecture here :
Courtesy : Image by www.pngegg.com
