11/19/2023

What is PDK DK in VLSI ?

November 19, 2023    



 Complete Design Kit:




Lets talk about Design Kit first. A design Kit is usually subdivided into three subsections : PDK or Process Design Kit, Init files or initiation files or initiation tools and IP kit or the Library. PDK consists of Tech file. Design Rule Manual, TCAD NXT-GRD, DRC, LVS, ERC, ESD,Antenna rules, Em_IR rules. PDK comes from foundry. Init-Files comes from foundry .  The IP Kit may come from foundry or foundry partners. The IP kit contains Standard Cell Library, essential semiconductor memories like SRAM/DRAM/NVM , Analog IPs like PLLS, high speed IPs or IO Pad IPs USB/MIPI/PHY etc. 

Init-Files:

Init Files are  Shell  script files related to tool initiatiion. BASH/TCSH Shell script Files.

1) .cshrc file for license setup. License demon , license path everything mentioned there.

2) .*rc file of the respective tool. That is configurartion file for different tools. 

3)  Project Specific Init File. If there are multiple projects in the company. preject specific Init-Files could be there. 

4) Path Inclusion File. These files contains tool installation path, license path or path of important files .

Process Design Kit (PDK):

It comes from foundry. All technological data that comes indicates compatible data or must-be-used data. 

Technology Data contains :

1) Tech File
2) Metal / Via / Contact Layers Information
3) Intrinsic/Extrinsic Silicon Layers Information
4) Layer names, layer/purpose pairs , layer-maps
5) Colors, fills and display attributes
6) Process Constraints
7) TCAD NXTGRD File
8) Human Readable Design Rule Manual (Usually comes in pdf format)

Process Design Kit (PDK):

Now lets take a look at the Physical Verification Decks of the PDK. Below checks are absolutely necessary before tapeout.

1) Design Rule Check (DRC)

2) Layout Versus Schematic (LVS) Check

3) Antenna and Electrical Rule Check

4) Electromigration (EM) Rules

5) IR Drop Rules

6) Aging Rule/Models 

7) EDA Tool Specific Rules


IP - Kit :

IP Kit contains  Standard Cell Library, Semiconductor Memories, High Speed IPs or Interface IPs and Analog IPS as mentioned below.

1. Standard Cell Library
  • Primitive Gates Library
  • Power Management Cells :  Isolation Cells,   Level Shifter Cells,   Retention Cells (FF) ,  Power Switch Cells
  • Special Cells: Tap Cells , Filler Cells , ECO Cells , Antenna Diode  De-Cap Cells , End-Cap Cells , Tie-Cells , Spare Cells
  • Power-Performance-Area (PPA) Based Architecture Variation of Cells
  • Track (Cell-Height) Based Architecture Variation of Cells
  • Verilog/VHDL/System-Verilog Views for Front-End
  • Timing Library (.lib) [ NLDM, CCS and ECSM ] [fast , typical , slow corner]
  • LEF/DEF/GDSII Views For Back-End
2. Semiconductor Memories:
  • Cache Memories
  • SRAM Compiler
  • NAND/NOR Architectural Variation of NVM Cells
  • DRAM Cells
  • Flash Memories
  • BRAM Memories
3. High-Speed / Interfaces
  • SATA IP
  • HDMI IP
  • IO-PAD IP
  • Network-On-Chip
  • Bluetooth IP
  • Ethernet IP
  • Serializer/Deserializer (SerDes ) IP
  • Universal Serial Bus (USB) IP
  • MIPI-Phy Families of IP

4. Analog IPs
  • Phased Locked Loop (PLL) IP
  • DC-to-DC Converter (DCDC) IP
  • Analog-To-Digital Converter (ADC)
  • Digital-To-Analog Converter (DAC)


Watch the video lecture here: 


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