The major challenge in the VLSI design are area, performance(frequency) and power consumption. In micro-powered battery operated portable devices as cell phones, smart watch and wearable medical devices the target is to keep the battery lifetime long and area/weight reasonable. In such devices leakage power during the off-state is a major power management concern. We already have entire episode on Low Power Design. To chisel higher performance from the same design, various optimization techniques are used. While achieve timing convergence and gain power,must not have any negative impact on the overall efficiency. Analysis and Optimization of overall timing is bare necessary to improve frequency/performance.
Power Optimization:
Performance Optimization:
Generally Timing closure is a combinational effort of :
(i) years spent on methodology development, script development, sign-off recipe development.
(ii) months of block-level and top-level final physical implementation.
(iii) a last set of several hundred manual noise and DRC fixes, along with a final multi-day pass of full-chip sign-off analysis and physical verification.
The nature of timing closure has changed as technology is shrinking. During low power designing, HVT cells , with high threshold voltage and low leakage power, are used. Due to this, transition time increases and it becomes challenging to achieve the timing closure. Hence it is important to have balanced use of HVT, SVT and LVT cells. Nowadays multi-million gate chips are used in order to increase the functionality in digital design. As the number of gates increase, routing becomes complex and many nets may detour. Detouring of nets adversely affect the timing closure of the design. A good floor plan avoid congestion and nets detouring to achieve timing closure. Cross-talk delay and noise are dominating which affects timing closure adversely. By double spacing between aggressor and victim net and shielding, cross-talk can be avoided.
Area Optimization:
Area Optimization does not always mean area shrinking. Source code modification (RTL description style) is done as synthesis tools are sensitive to the coding style. Identify static signals (e.g. registers enables), and simplify them. Pack the registers with orphan logic gates, that were inferred as stand-alone gates by the ASIC synthesis tools. Floorplanning is the first step of the backend or physical design in the VLSI design flow. It is a design step to estimate the chip area and wirelength by considering the optimal placement of digital blocks and their interconnections.The classical floorplanning methods are normally used for increase packing density to minimize the total chip area. They do not consider chip boundaries, i.e outline-free, but modern floorplanning methods deal with fixed-outline floorplanning. Floorplan also needs to consider whether there is sufficient routing area between the blocks so that the routing algorithms can complete the routing task without experiencing routing congestion.
Watch the video lecture here:
