VLSI Milestone & Gate Material :
Over last Few decades CMOS process has seen a strange transition from metal gate to Polysilicon gate to again metal gate. In earlier days Aluminium was used as gate material. Due to advantages of self aligned process industry moved to incorporation of Poly Silicon as gate material. With progressing node, again metal gate isintroduced in process. In this article we will discuss about the reasons behind these transitions.
What is Poly Silicon?
Polysilicon, poly-Si, multicrystalline Silicon,or polycrystalline silicon, is a material consisting of a number of smaller crystals or crystallites. It is made up of multiple small silicon crystals and is used in the solar and electronics industries.
Polycrystalline silicon is very popular in the solar industry since it is used in the production of solar cells, a key component in manufacturing solar panels. It has also found uses in various electronic devices, ranging from small components to automotive controls. There are three main methods to produce high-quality Poly-Silicon for use in different applications : The modified Siemens process, The fluidized bed reactor (FBR), process, The upgraded metallurgical-grade (UMG) silicon process.
Why Poly -Si Used as Gate?
In the early days Aluminum, was preferred for gate material of MOSFET. Later on, Poly -Si has gained preference.
Reasons behind it are:
1. CMOS fabrication involves high temperature process steps. Poly- Si melts at 1414 ˚C whereas Aluminum Melts at 660 ˚C. Diffusions and Anneals of Silicon Typically Require Around 1000 ˚ C causing any Aluminum present during processing to melt.
2. Poly Si supports self-aligned gates development. In case of Al gate Source and Drain must be formed prior to forming the gate. Causes misalignment of the Gate to the Source and Drain. To assure the overlapping of gate to the source and drain size of the gate is increased. Such misalignment of Gate cause substantial variability. This gate must be made approximately 3 times larger than the space between the source and drain to insure that this whole region is spanned. This results in a slow device the characteristics of which are strongly affected by the random misalignment of this gate element.
3. Undoped polysilicon has high resistivity. It is doped in such a way that its resistance is reduced. Heavy doping of Poly-si generates highly conductive gates required to form the device
4. Polysilicon is a Semiconductor its work function can be modulated by adjusting level of doping. Threshold voltage of MOSFET is related with work function difference between gate and channel material. The work function of a semiconductor qϕs is the energy difference between the vacuum level and the Fermi level and that varies with thedoping concentration. For a given metal with a fixed work function qϕm , work function difference qϕms ≡ (q ϕm – q ϕs) will vary depending on the doping of the semiconductor. Work function of Poly-Si can be varied with level of doping.
5. With proceeding nodes device dimensions reduced and their operating voltages also scaled down. For such situatiion low Vt MOSFETs required. Poly-Si gate MOSFET has lower Vt. Since Highly doped Poly -Si is used as gate material, its work function can be modulated by adjusting the level of doping.
6. Fabrication steps with Poly Silicon are less. Fabrication process specially mask creation and aligning is a critical and expensive process.
Why Self Aligned process is so preferred?
Performance Benefits :
1. Reduce the overlap capacitance.
2. Reduce the variability of overlap capacitance.
3. Reduce the threshold voltage of the PMOS transistors being used in MOSFETs at that time by 1.1 V
4. Workfunction difference between P-Doped Poly-Si gate and the substrate 1.1V lower than for Al
5. Lowered threshold voltage by 1.1 V or 30%
6. Increased speed by 3 to 5 times at same power dissipation
7. Reduced power by 3 to 5 times at same speed
8. Substantially reduced variability in device performance
9. Reduced silicon area and cost by approximately one half
10. Gate area substantially reduced by smaller gate
11. Polysilicon used as local interconnect increasing
routability and reducing area
12. Enabled use of Phosphosilicate Glass/PSG, which
requires higher temperature processing
Poly Depletion Effect :
Undoped Poly-Si has high resistivity. Highly doped Poly-Si is a good conductor. A heavily doped film of Poly-Si is used as the gate electrode material. Electrically active dopant concentrartion is usually less than 1X10^23 cm-3 . Poly-Si gates must be considered as semiconductor rather than a metal. Polysilicon Depletion effect is the phenomenon in which unwanted variation in Vth is observed when polysilicon is used as gate material. That leads to unpredictable behavior of the electronic circuit.
When voltage applied at gate terminal (+ve voltage in n channel MOSFET and -ve voltage in p-channel MOSFET)free carriers in highly doped polysilicon move towards the gate electrode and zone near the oxide get depleted of free carriers. This is basically depletion of polysilicon. This depleted zone contributes in effective gate oxide thickness and capacitance of this zone is added with gate oxide capacitance. This effect is known as polydepletion effect. Polydepletion leads effective increase of the dielectric thickness and an increase of the threshold voltage. Because of this High-k Dielectric/metal gates were introduced to solve the issue.
High-K Material & Poly-Si Gate:
At smaller nodes, leakege in MOSFET is predominant. Higher conductivity in the gate has also become important as the oxide dielectric layers cannot be shrunk any further to increase speed. As a result dielectric material with high k value is used as gate oxide. Poly Si and High-K material interact at high temperatures - creating Salicides. This thin (1–4 nm) layer have undesirable and unnecessary electrical impact on device performace. The compatibility and integration of high k dielectrics with polysilicon in existing CMOS process,within appropriate thermal budgets is one of the critical issues to implement high k materials into sub 0.1 um VLSI device fabrications. Various interfacial reactions take place during poly deposition at higher temperature (> 500 C). Interfacial reactions can be further enhanced during subsequent source/drain anneal where temperarture rise upto ~1000 oC in CMOS processing. Another issue with PolySi/High-K combination is that threshold voltage become unacceptably (specially at advanced node) high. As a result , metal gates are used with a high-k dielectric CMOS processing.
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Courtesy : www.pngegg.com
