Major Device Milestone in VLSI :
1. new structure like FinFET, SOI, Nano Sheet FET
2. new material like Strained-Si, High-k dielectric
3. new interconnect material like Cu
Advantages of SiO2 :
Silicon dioxide is the main reason that microelectronics uses Si technology and not another semiconductor. As a semiconductor, Si has average performance, but in most respects SiO2 is an excellent insulator. SiO2 can be made from Si simply by thermal oxidation, whereas every other semiconductor (Ge, GaAs, GaN, SiC…) has a poor native oxide or poor interface with its oxide. SiO2 is amorphous, has very few electronic defects and forms an excellent, abrupt interface with Si. SiO2 can be etched and patterned to a nanometer scale. Its only problem is that it is possible to tunnel across it when very thin.
What are Low-K & High-K Dielectrics?
The dielectric constant, k, is a parameter defining ability of material to store charge. The k value of SiO2 is 3.9 and in si technology it is considered as reference. Dielectrics with k>3.9 are referred as “high”-k and dielectrics with k<3.9 are defined as “low”-k dielectrics. In state-of-art VLSi technology both high- and low-k dielectrics are needed and used for different reasons.
Need for high-k dielectric:
- SiO2 has been used as a gate oxide material for decades.
- The thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance, drive current and raising device performance. As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability.
- Use of high-k dielectric instead of SiO2 leads to increased gate capacitance while keeping gate oxide thickness fair enough so that leakage effects are reduced.
Need for low-k dielectric:
-In digital circuits, insulating dielectrics separate the conducting parts (wire interconnects and transistors) from one another. As components have scaled and transistors have gotten closer together, the insulating dielectrics have thinned to the point where charge build-up and crosstalk adversely affect the performance of the device. To reduce parasitic capacitance low-k dielectric is used instead of SiO2.
Why High-k Dielectric ?
Over last few decades scaling of MOSFET dimension has been been viewed as an effective approach to enhance transistor performance as predicted by Moore’s law. Scaling includes Gate Oxide thickness reduction. Reduction in the thickness of silicon dioxide gate dielectrics has enabled increased numbers of transistors per chip with enhanced circuit functionality and performance at low costs. As we approached sub-45 nm node, the effective oxide thickness (EOT) of the traditional silicon dioxide dielectrics are required to be smaller than 1 nm, which is approximately 3 monolayers and close to the physical limit. Such thin layer of Silicon is prone to high gate leakage current due to the obvious quantum tunneling effect at this scale. To continue the downward scaling, dielectrics with a higher dielectric constant (high-k) are being suggested as a solution to achieve the same transistor performance while maintaining a relatively thick physical thickness.
Dielectric Conductance & Breakdown :
Performance of MOS devices depends on the breakdown properties and the current transport behaviors of the gate dielectric. Ideally in an MOS structure, the conductance of the dielectric is assumed as zero. However in real world situation under high electric field/ temperature there is some carrier conduction. Tunneling is the conduction mechanism in insulators. Tunneling is a quantum mechanical phenomenon in which electron wave function can penetrate a potential barrier.
There are 4 different mechanism :
1. direct tunneling,
2. F-N tunneling,
3. Schottky Emission ,
4. Poole Frankel Emission
Under large bias, tunneling current flows through dielectric. When energetic carriers move through the insulator, defects are generated randomly in the bulk of the dielectric film. If number of defects are high enough to form a continuous path connecting the gate to the semiconductor, a conduction path is created and dielectric breakdown occurs.
Essential Qualities of High-k Dielectrics:
1. K value, band gap and band offset : To get high capacitance k value must be over 12, preferably 25–30. High-k value means, the dielectrics will have a reasonable physical thickness to prevent gate leakage. The layer must not be too thick to hamper physical scaling when achieving the target EOT. On the other hand, a very large k value is undesirable in CMOS design because they cause unfavorable large fringing fields at the source and drain regions. If a high-k dielectric can replace SiO2, the dielectric thickness (Tk) increases proportionally to keep the same dielectric capacitance. A figure of merit to judge a high-k gate dielectric layer is the equivalent oxide thickness, defined as EOT = (ε1/ε2)T where ε1= 3.9 , ε2 = k value of High-k material, T= High-k dielectric thickness.
2.Thermal stability : In present CMOS processes, the gate stacks must undergo rapid thermal annealing . This requires that the gate oxides must be thermally and chemically stable especially with the contacting materials. Additionally, oxides should not react with water. Among many high k dielectrics, HfO2 has both a high k value as well as chemical stability with water and Si.
3. Crystallization temperature : Amorphous materials are preferred to crystalline ones, owing to the absence of grains and good diffusion barrier properties. The grains present in the crystalline systems can often be the pathways for dopants diffusion and breakdown. Unlike SiO2, high-k oxides usually have low crystalline temperature and can easily crystallize when subjected to RTA. In particular, HfO2 and ZrO2 crystallize at much lower temperatures at ~400 oC and ~300 oC, respectively. According to the above factors, the approach to improve the crystallization temperature of HfO2 and ZrO2 should be considered. The crystallized HfO2 has a much lower leakage current.
4. Interface Quality : The interface between the high-k dielectrics and Si substrate must have the highest electrical quality and flatness, absence of interface defects, and low interface state density Dit. Bad interface quality can cause high fixed charge density, inducing a large shift in the flat band voltage (Vfb) which severely reduces the performance and reliability of the transistor.
5. O2 and dopant diffusion through the grain boundary
6. Compatibility with the gate electrode
7. Density of interface states comparable to SiO2
8. Low lattice mismatch and similar thermal expansion coefficient with Si
9. Mobility comparable to SiO2
High -k/Metal Gate:
To continue the downscaling, dielectrics with a higher dielectric constant (high-k) are being suggested. Many candidates of possible high-k gate dielectrics have been suggested to replace SiO2 and they include nitrided SiO2, Hf-based oxides, and Zr-based oxides. Hf-based oxides have been recently highlighted as the most suitable dielectric materials because of their comprehensive performance. One of the key issues regarding new gate dielectrics is the low crystallization temperature. Due ti this reason, it is difficult to integrate them into traditional CMOS processes. To solve these problems, additional elements such as N, Si, Al, Ti, Ta and La have been incorporated into the high-k gate dielectrics, especially Hf-based oxides. For the gate electrode, both poly-Si and different metals have been investigated along with high-κ dielectrics. The combination of a high-κ dielectric and a poly-Si gate is not suitable for high- performance logic applications since the resulting high-κ/poly-Si transistors have high threshold voltages and degraded channel mobility, and hence poor drive current performance. It has been proposed that the high threshold voltage is caused by Fermi level pinning at the poly-Si/high-κ dielectric interface and that Fermi level pinning is most likely caused by defect formation at that interface. It has been demonstrated both experimentally and theoretically that surface phonon scattering in high-κ dielectrics is the primary cause of channel mobility degradation. Significantly, metal gate electrodes are effective for screening phonon scattering in the high-κ dielectric from coupling to the channel when under inversion conditions. This results in improved channel mobility.
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