VLSI Milestone & Multi Level Metallization:
Moore’s law has been driving and guiding force for last few decades. With progressing node circuit complexity has increased. Reduced dimension has made short channel effect, parasitic effect more severe. To keep up with the pace of scaling, new material, new device structure was found and introduced. Higher package densities and design flexibility was achieved by increasing interconnect layers. To increase circuit performance different materials incorporated at different part of total interconnect network. Research led us to new inter-metal dielectric layer or low- k dielectric layer.
Metallization:
Conductive films provide electrical interconnection among devices as well as the outside. Three categories : gate, contact and interconnect.
Polysilicon and Silicide are frequently used for gate connection , Al/Cu are used as contact and second-level interconnection to the outside. In some cases, a multiple-layer structure involving a diffusion barrier is used. Titanium /platinum/ gold or titanium / palladium / gold is useful in providing reliable connection to external components.
Circuit speed is controlled by the resistance and capacitance of the interconnect. Metallization is deposited by either physical vapor deposition (PVD) or chemical vapor deposition (CVD).
Desired properties of the metallization for ICs:
1. Low resistivity , easy to form and easy to etch for pattern generation
2. Should be stable in oxidizing ambients and oxidizable
3. Mechanical stability, good adherence, and low stress
4. Surface smoothness
5. Must be stable throughout processes including high temperature sinter, dry/wet oxidation, gettering, passivation, and metallization
6. No reaction with final metals
7. Should not contaminate devices, wafers, or working apparatus
8. Good device characteristics and lifetimes
9. For window contacts - low contact resistance, minimal junction penetration, and low electro-migration
Multi Level Metallization:
RC Time Delay : As technology progresses, Ls decreases. RC delay increases.
Lower resistivity metal for interconnect wiring – Cu Interconnect
Lower dielectric constant material for the interlayer dielectric - Low-K
Contact Resistance : Low contact resistance to semiconductor device
Immunity to EM : reliable long-term operation
State-of-art ICs have millions of transistors and connecting them all to some voltage and current supply without wires crossing is a real challenge. 3-D network of interconnections is called Multi Level Metallization. Multi-level metallization increases interconnect capacity and reduces resistance and capacitance.
Stretches over several planes and isolated by the insulating dielectric layers. Interconnected by the wiring through the holes in the dielectric planes.
Benefit of Multi Level Metallization:
- Reduced interconnection lengths and reduced RC,
- Higher package densities and design flexibility
Components of Multi Level Metallization:
Components of Multi Level Metalization Circuit are:
(i) Interconnects,
(ii) Contacts,
(iii) Vias,
(iv) Intermetal Dielectric ,
(v) Passivation.
Active devices are electrically connected to each other. They are connected to the outside world through their I/P and O/P on bonding pads. Contact is connection to source, drain or poly. Vias are connections between interconnect levels. Interconnects are separated from each other by dielectric layers. Vias connect interconnects through these layers. These components are part of the metallization/backend/BEOL. Local interconnects are the first/lowest level of interconnects. They are small and short and connect gates, sources and drains. Poly Si, Silicide, TiN, W (Tungsten) can act as local interconnect. Local interconnects can afford to have higher resistivities since they do not travel very long distances. They must be able to withstand higher processing temperatures. Global interconnects are usually made of Al/Cu. They are above the local interconnect level. Global interconnects are thick, long, and widely spaced. They travel longer distances, between different devices and different parts of the circuit, and therefore are always metals with lower resistivities. After completion of metallizationa passivation layer is formed to protect the internal semiconductor devices. The passivation layers are typically formed with deposition of an oxide layer and a nitride layer.
Interconnect Material : Aluminium(Al)
Aluminum interconnects were used as the standard for a long time in chip-making. In the late 1990s, chip-makers switched to Cu.
=>Advantages of Aluminium :
- It is a good conductor
- It can form mechanical bonds with silicon
- It can form low resistance, ohmic contacts with heavily doped n-type and p-type silicon
- Corrision resistant
=>Disadvantages of Aluminium :
- Low melting point
- Junction Spiking
- Electromigration
- Stress migration
=>Junction Spike :
Use of pure aluminum leads to a diffusion of siliconinto the metal. Si reacts with the metallization at only 200–250 °C. This diffusion of Si causes cavities at the interface of both materials which are then filled by Al. This leads to spikes which can cause short circuits if they reach through the doped regions into the silicon crystal beneath. Size of these spikes depends on the temperature at which the Al was deposited. To avoid spikes a deep ion implantation can be introduced at the location of the vias. Thus the spikes do not reach into the substrate. An alloy of aluminum and silicon can be used (silicon 1–2 %). Since Al now already contains silicon there will be no diffusion out of the substrate. A barrier of different materials such as titanium, titan nitride or tungsten is deposited as barrier layer.
=>Electromigration:
Electro-migration is the movement of atoms in a metal film due to momentum transfer from the electron carrying the current. Under high current density condition metal atom movement creates void in some region and metal pileup or hillock in the other regions. As a result either open ckt. or short ckt. happens in interconnect networking. A common practice to prevent Em is to use an i.e. alloying with copper (Al with 0.5%Cu).
=>Stress Migration:
Interconnect Material : Copper(Cu)
Use of diffusion barriers and adhesion promoters :
Unlike Al metallization, Cu cannot be easily patterned by reactive ion etching (RIE). Hence, to fabricate Cu interconnects, a different process flow which is called “damascene” process has been developed, including “single damascene” and “dual damascene” processes.
Single/Dual Damascene Process :
Low K Inter Metal Dielectric:
Lower-k dielectrics are grouped as ,(i) Ultralow-k (k < 2.2-2.4) or (ii) low-k (2.4 < k < 3.5). These materials can be deposited either by a spin-on route (spin-on dielectrics or SODs) or by a chemical vapor deposition (CVD) or plasma-enhanced PECVD technique. Their final properties are influenced by both the deposition method and post deposition treatment such as anneals or chemical treatments.
