Performance Boost by FinFET : VLSI Milestone Episode-5 ~ TechSimplifiedTV.in

VLSI Milestone & FinFET

Scaling degrades perfomance of deep submicron MOSFET devices. Vd controls the channel and Vg losses control over channel. Vg is unable to shut off the channel completely in the off-mode of operation, which leads to an increased Ioff between drain and Source. Multiple-gate field-effect transistors (MGFETs), emerged as an alternative to planar MOSFETs. MGFETs demonstrate better control over channel and MOSFET performance. Among all MGFETs, FinFETs (a type of DGFET) and Trigate FETs (another popular MGFET with three gates) have emerged as the most desirable alternatives to MOSFETs due to their simple structures and ease of fabrication.

Leakage Current and Novel Structures:

Gate cannot control leakage path far away from gate. SOI MOS structure reduce leakage and chance of latch up. Addition of another gate can increase control over channel. The main idea of a DG MOSFET is to control the Si channel more efficiently compared to planar MOSFET. Si channel width is usually kept small and voltage is applied on both sides of channel. Such a structure and operation effectively suppress short channel effects and leads to higher currents as compared with a MOSFET having only one gate.

Evolution of Different Multi Gate FET:

What is FinFET?

A multigate non-planar Field Effect Transistor. Channel is wrapped with gate from two/three sides. FinFET is Fin-Shaped-FET. Fin is a body part of fish which stick out of its body. A Silicon Fin forms its body. The channel of the FinFET is vertical.

Lg = gate length , Tsi = fin thickness , Hfin = fin height

Can be built over bulk silicon or SOI wafer.

For double-gate: W = 2 ∙ Hfin ; For tri-gate: W = 2 ∙ Hfin + T

Different Types of FinFET:

Two types of Gate design :

i. Double Gate FinFET

ii. Triple Gate FinFET

Two types of gate connection :

i. Shorted Gate FinFET (SGFinFET) : 3 terminal device.

Front and back gate are physically connected/shorted. Electrostatics of channel is controlled by both gates together.

ii. Independent Gate FinFET (IGFinFET) : 4 terminal device.

Gates are isolated. Different voltages can be applied to gates. This flexibility is very useful.

Two types of Wafer :

i. Bulk FinFET

ii. SOI FinFET

Planar MOSFET vs FinFET :

FDSOI MOSFET vs FinFET

Bulk FinFET vs SOI FinFET

Corner Effect:

Corner Effect :

Charge accumulation at corners or areas with higher curvature are higher (basic Physics). So electric field at corners are higher. Same rule follows for FinFET. Charge accumulation and electric field higher at corners. High channel doping create premature inversion at the corners due to charge accumulation. Electric field coupling in device corners results in lower threshold voltage of corner regions. Corners are turned on earlier (at lower gate voltages) than the other parts of the channel. This doesn’t exist in the other parts of thesilicon/silicon-dioxide interface. This means that different regions of the transistor with high electron density are activated at different gate voltages. This premature inversion at the corners of the triple gate FinFET degrades the sub-threshold characteristics of the FinFET which results in higher off state leakage. The corner effects must be suppressed to avoid leakage currents. There are various techniques available toeliminate the corner effects, such as, reduction in doping concentration in channel, and corner rounding etc.

Process Variations :

FinFETs suffer from process variations. Due to small dimensions and lithographic limitations, FinFETs are subjected to physical fluctuations, like variatioins in gate length , fin- thickness , gate-oxide thickness and gate underlap . Gate oxide is on the etched sidewall of the fin, and may suffer from nonuniformity. The degree of nonuniformity depends on the line-edge roughness (LER) of the fin.

FinFET Fabrication Flow – 1 & 2

Wafer Preparation:

Cleaning of wafer. Base is a lightly p-doped substrate with a SiN (silicon nitride) hard mask and a patterned resist layer on top .

Fin etching :

Highly anisotropic etch process is used. The etch process is time based as there is no stop layer on a bulk wafer. In 22 nm process the width of the fins might be 10 to 15 nm, whereas the height would must be twice of that or more.

Oxide deposition :

To isolate the fins from each other a oxide deposition is

done.

Planarisation :

Planarisation is done. This is the process to increase the

smoothness or planarity of a wafer through process like CMP.

Recess etch :

Another etch process is needed to recess the oxide film to form a lateral isolation of the fins.

Gate oxide :

Gate oxide is deposited on top of the fins by thermal oxidation to isolate the channel from the gate elctrode. Since the fins

are still connected underneath the oxide, a high- dose angled implant at the base of the fin creates a dopant junction and

completes the isolation (not illstrated).

Gate Formation :

A highly n+ doped poly silicon layer is deposited on top of the fins, thus up to three gates are wrapped around the channel:

one on each side of the fin, and - depending on the thickness of the gate oxide on top - a third gate above.

Since there is an oxide layer on an SOI wafer, the channels are isolated from each other anyway. In addition the etch process of the fins is simplified as the process can be stopped on the oxide easily.

FinFET Advantages:

Better control over the channel
Suppressed short-channel effects
Lower static leakage current
Faster switching speed
Higher drain current (More drive-current per footprint)
Lower switching voltage
Low power consumption

FinFET Disadvantages:

Self-Heating Effect
Quantized device-width. It is impossible to make fractions of the fins, whereby designers can only specify the devices’ dimensions in multiples of whole fins.
Higher parasitics due to 3-D profile
Very high capacitances
Corner effect
High fabrication cost

Big Houses Who Work With FinFET Technology :