In this extensive article, we thoroughly explore various essential aspects related to VLSI technology and SOI MOSFET. The discussion commences with an introduction, providing viewers with an initial overview, followed by a helpful chapter index for easy navigation through subsequent topics. The focus then shifts to VLSI milestones and the significance of SOI MOSFET. A detailed exploration of SOI follows, including an explanation of what SOI is and an in-depth examination of its fabrication process in three parts. The video proceeds to unravel the reasons behind VLSI's adoption of SOI, contrasting it with the drawbacks of Bulk MOSFET. Further insights into the advantages of SOI are provided, followed by an intricate analysis of the performance of SOI MOSFET. Specific attention is given to the phenomena of Kink Effect and strategies for reducing Floating Body Effect. The video concludes with a comparative exploration of FDSOI vs PDSOI, offering viewers a comprehensive understanding of the intricate aspects of SOI MOSFET technology in the field of VLSI.
VLSI Milestone & SOI MOSFET
Moore's law has been the main driving force for last few decades. Device dimension reduced and performance got boost. Down scaling has resulted in short channel effect. New device structure like SOI has been introduced. Global Foundry has developed SOI solutions for high-growth, high-volume wireless and WiFi markets. FD-SOI is a suitable technology for new standards for IoT, automotive and mobile connectivity applications.
What is SOI?
SOI or Silicon-on-Insulator refers to a technology where MOS device is fabricated on silicon-insulator-silicon substrate rather than conventional silicon. SOI MOSFET is fabricated as three layered device,the bottom most layer is the substrate which is lightly doped. The uniform buried layer of silicon dioxide which is called as buried oxide layer (BOX), supporting substrate or handle wafer or base wafer. The SOI is also a 4 terminal device source, drain, gate and the body. In SOI based devices Silicon junction and channel area are above electrical insulator like SiO2. Choice of insulator depends on application. Sapphire is used for high performance radio frequency (RF) and radiation sensitive application. SiO2 is used for microelectronics applications to minimise short channel effect. The width of the silicon film decides whether the SOI is fully depleted or partially depleted. If the width of SOI film laid over the buried oxide is thin, the device is said to be fully depleted or FDSOI. If the width of the SOI film is thick, it is said to be partially depleted or PDSOI. The thickness of the SOI layer for an FD-SOI MOSFET is usually about one-third the effective channel length in order to avoid a punch-through current. Thickness of BOX varies depending on application.
SOI Fabrication Process :
There are few unique ways to fabricate SOI Wafers, such as : SOS (Silicon On Sapphire ), Bonded and Etch back SOI, SIMOX (Separation By Implanted Oxygen), ELTRAN (Epitaxial Layer TRANsfer) , Smart-Cut .
i. Silicon on Sapphire (SOS) :
SOS wafers are formed by depositing Si onto the sapphire substrate at very high temperatures. Very pure sapphire crystal is grown in a controlled lab environment and the Si can be cleanly deposited on the surface of the sapphire wafer.
ii. Bonded and Etch back SOI (BESOI) :
iii. SIMOX Method :
iv. SmartCut Fabrication Process :
v. ELTRAN (Epitaxial Layer TRANsfer):
Why VLSI Adopted SOI?
i. DIBL :
ii. Punch Through :
It a break down mechanism. Occurs when the sum of depletion layer width for source and drain junctions is comparable to the channel length. The depletion region of the drain and source junctions gradually merge together as the drain voltage is increased, causing current to flow irrespective of Vg at high Vd.
iii. CMOS-Latch Up :
Parasitic BJTs in a CMOS structure forms feedback loop and create a PNPN structure. Such latched up condition create low impedance path between Vdd and Vss. High current flows and the IC gets damaged.
iv. Junction Capacitance :
Cj = Junction Cap. Cd= Depletion Cap.
Cg = Gate Cap. Cov =Overlap Cap.
v. Leakage Current :
Gate Current Tunneling , Hot Carrier Injection
Subthrehold Current, Reverse Bias Jn. Current,
Gate Induced Drain Leakage, Channel Punch Through Current
Advantages of SOI :
SOI MOSFETs have a bunch of advantages compared to to trheir Bulk Silicon counterpart. Such as :
1. Reduction in : 1. Drain /source parasitic capacitances, 2. Delay,dynamic power consumption, 3. Leakage current.
2. Due to an oxide layer, the threshold voltage is less dependent on back gate bias compared to bulk CMOS. This makes the SOI device more suitable for low power applications.
3. SOI devices have no latch-up problems as there is no substrate to form PNPN structure.
4. Diffusion capacitance reduction (since bottom touches insulator).
5. SOI devices have excellent radiation hardness to alpha particles, neutrons, and other particles. Alpha particles are generated by small amounts of radioactive elements in IC materials.
6. SOI allows more devices per die area due to absence of wells and the possibility of direct contact of the source-drain diodes in the NMOS and PMOS transistors.
7. BOX coupled with ground plane (GP) suppress fringing electric fields through the BOX and substrate. So front-gate-to-channel control increases and DIBL lowers.
8. Faster device operation (speed/power product) due to reduction of parasitic capacitance (primarily due to reduced source-drain junction capacitance, but also from gate-to-substrate capacitance and metal-to- substrate capacitance).
9. Performance improvement happens equivalent to next technology node without scaling (e.g., performance of 0.25 micron devices on SOI wafers equivalent to performance of 0.18 micron devices on bulk wafers) .
10. Potential to simplify device fabrication steps. Fewer masks and ion implantation steps, made possible by the elimination of well and field isolation implants. Less complex (costly) lithography and etching required to achieve next-generation performance.
Performance of SOI MOSFET :
i. Threshold Voltage :
A thick-film SOI device, behaves like a bulk device due to absence of interaction between the front and back depletion regions, the threshold voltage is same as in a bulk device. For a thin- film SOI device, the threshold voltage is a function of the different possible steady-state charge conditions at the back interface.
ii. Body Effect :
In an SOI transistor, the body effect is defined as the dependence of the threshold voltage on the back-gate bias. In a thick film device, the body effecty (i.e. back-gate effect) is negligible due to absence of coupling between the front and back gate.
iii. Floating Body Effect : Floating body effect (FBE) is the major parasitic effect in SOI-MOSFETs and is a consequence of the complete isolation of the transistor from the substrate. The effect is related to the built-up of a positive charge in the Si body of the transistor, originating from the holes created by impact ionization. This charge cannot be removed rapidly enough, primarily because no contact with the Si film (body) is available. Self heating, bipolar currents and kink effect are said to be the major disadvantages of SOI technology when the body is left floating.
iv. Floating Body and Parasitic Bipolar Effects:
The presence of a floating volume of silicon under the gate is the origin of several effects, generically referred to as floating body effects. There exists a parasitic bipolar transistor in the MOS structure. If we consider an n-channel device, the N+ source, the P-type body and the N+ drain indeed form the emitter, the base, and the collector of an NPN bipolar transistor, respectively. In a bulk device, the base of the bipolar transistor is usually grounded by means of a substrate contact. But, due to the floating body in an SOI transistor, the base of the bipolar transistors is electrically floating. This parasitic bipolar transistor is origin of several undesirable effects in SOI devices.
v. Self Heating Effects:
Due to thermal isolation of substrate by the buried insulator in an SOI transistor, removal of excess heat generated by the Joule effect become critical. It leads to substantial elevation of device temperature. The excess heat mainly diffuses vertically through the buried oxide and laterally through the silicon island into the contacts and metallization. Due to the relatively low thermal conductivity of the buried oxide, the device heats up to 50 to 150C. This increase in device temperature leads to a reduction in mobility and current drive, thus degrading the device performance over a period of time.
vi. Kink Effect :
The kink effect is appearance of a kink in the output characteristics of an SOI MOSFET under strong inversion. The kink is very strong in n channel transistors, although absent from p-channel devices. In a thick-film or n-channel PD SOIMOSFET. When Vd is high enough, the channel electrons can acquire sufficient energy in the high electric field zone near the drain to create e-h pairs, due to an impact ionization mechanism. The generated electrons move into the channel and the drain, whereas the holes, which are majority carriers in the p-type body, migrate towards the place of lowest potential i.e., the floating body. The injection of holes into the floating body forward biases the source-body diode.The increase of body potential gives rise to lowering of threshold voltage and source-body potential barrier. More minority carriers are able to flow from source to the channel, thereby causing an excess drain current and producing many more pairs through the avalanche process. This positive feedback results in a sudden increase in Id or kink in output characteristics.
More on Kink Effect
FDSOI MOSFET and Kink Effect :
The electric field near the drain is lower in the FDSOI than in PDSOI. As a result, less electron-hole pair generation takes place in the fully depleted device. Also, in FDSOI, the source-to-body diode is already forward biased due to the full depletion of the film, and therefore, holes can readily combine in the source without having to raise the body potential there. That is why FDSOI is free of kink effect.
P-Channel SOI-MOSFET and Kink Effect :
The p-channel devices are free of kink effect because coefficient of electron-hole pair generation by energetic holes is much lower than that by energetic electrons. The kink effect is not observed in bulk devices as the majority carriers generated by impact ionization can escape into the substrate or to a well contact. The kink effect can be eliminated from the partially depleted SOI MOSFETs if a body contact is provided for removal of excess majority carriers from the device body.
Reducing Floating Body Effect
Body Contact :
Contacting silicon underneath the gate region to the ground effectively suppresses the kink effect as well as the parasitic lateral bipolar effects. Several schemes exist to provide the transistor with body contact. It consists of a P+ region which is in contact with the P-type silicon underneath the gate.
Source Body Tie Structure:
A more compact method, source body tie structure. P+ body ties are created on the side of the N+ source diffusion. If the device width is large, additional P+ regions can be formed in the source (such that a P+ N+ P+ N+ structure is introduced). Such a device has the main drawbacks of being asymmetrical (source and drain cannot be switched), and the effective channel width is smaller than the width of the active area.
FDSOI vs. PD SOI:
FDSOI devices are naturally free from kink effect .FD SOI has an enhanced sub-threshold swing, S . Therefore FD devices operate faster because of a sharper sub- threshold slope, and a reduced threshold voltage that allows for faster switching of the MOS transistors. These transistors also have increased drive currents at relatively low voltages. Fully-depleted SOI devices have the highest gains in circuit speed, reduced power requirements and highest level of soft-error immunity. Interface coupling effect affects operations of FDSOI. their operation. The interface coupling is inherent to fully depleted SOI devices, where all parameters (threshold voltage, trans-conductance, interface-trap response etc.) of one channel are insidiously affected by the opposite gate voltage (at the buried oxide). The threshold voltage fluctuation due to SOI thickness variation is one of the most serious problems in FD SOI MOSFETs. PDSOI devices are built on a thicker silicon layer and are simpler to manufacture. Most design features for developing PD devices can be imported from the bulk silicon devices and used in the SOI environment with only modest changes. This makes circuit redesign for the PD devices simpler than for the FD microcircuits.
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