Manufacturing CMOS circuit is a huge task. A small variation in process parameter can impact device performance. and introduce variability. In this article we have discussed how variability art different stage of CMOS manufacturing impact the final performance, how variability leads to PVT corners and how we model them.
In this article , comprehensive exploration was undertaken, delving into various aspects surrounding the construction of CMOS technology. The discussion touched upon the intricate challenges inherent in CMOS development, emphasizing the significance of addressing variability and the diverse levels of abstraction involved in the process. Notably, the discourse delved into the critical factors contributing to process variation, including voltage (V) and temperature (T) fluctuations, and the essential concept of design corners. Furthermore, the presentation meticulously elucidated the sources of process variations, categorizing them into distinct segments for thorough examination. The subsequent segments of the discussion meticulously examined the impacts of process variations on crucial parameters such as carrier mobility, Cox, Vth, W, L, yield, delay, and energy consumption, shedding light on the multifaceted ramifications across these domains. Moreover, the discourse also delved into the analysis methodologies essential for comprehensively studying variability, as well as the crucial aspect of modeling variability for accurate prediction and optimization within CMOS technology.
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There are three different sources of variation :
a. Process Variation [P]
b. Supply Voltage [V]
c. Operating Temperature [T]
Aim is to design a circuit that operate reliably over all extremes of P, V and T. Causes poor yield and circuit performance.
Variability and Level of Abstraction:
Fabrication process steps such as oxidation, ion implantation, lithography, chemical-mechanical planarization (CMP) introduce variability in device. Random variations in operating conditions such as the temperature and the power supply voltage (Vdd ) increases with circuit clock frequency leading to circuit performance variations. This degrades yield and increase production costs. Variation of performance metric of a circuit like delay, dynamic power and static power consumptions ultimately propagate their negative influence on the overall performance of a Chip.
Process Variation (P):
Process Variations classified as :
1. Lot-to-lot (L2L) [Lot is batches of wafer ]
2. Wafer-to-wafer (W2W )
3. Die-to-die (D2D), inter-die, or within-wafer (WIW )
4. Within-die (WID) or intra-die
Variability in lot-to-lot, wafer-to-wafer and chip-to-chip are almost equally applied to every transistor on the chip. These Inter-Die variations,are called “global variations”. The remaining within-chip or Intra-Die variations referred as “local variations.” Global and local variations must be modeled accurately. That helps in estimating the power and performance scaling with circuit complexity. Local variations get averaged out for large number of transistors or long critical paths. Global variations usually add up and shift the average power/performance of the entire chip. D2D variations make one chip faster/slower than another. WID variations become important in nano-meter processes.
Voltage (V) & Temperature (T) Variation :
Systems are designed to operate at a nominal supply voltage, but this voltage may vary for many reasons including tolerances of the voltage regulator, IR drops along supply rails, and di/dt noise. Typically the supply is specified at ±10% around nominal at each logic gate. The supply varies across the chip as well as in time. Speed is proportional to operating voltage VDD and this leads to ±10% delay variations. As temperature increases, drain current decreases. The junction temperature of a transistor is the sum of the ambient temperature and the temperature rise caused by power dissipation in the package. This rise is determined by the power consumption and the package thermal resistance. Ambient temperature ranges for parts specified to commercial, industrial, and military standards. Temperature varies across a die depending on which part dissipate the most power. The variation is gradual, so all circuits in a given 1 mm diameter see nearly the same temperature.
Design Corners:
The collective effects of process and environmental variation can be lumped into their effect on transistors: typical (also called nominal ), fast, or slow. When these processing variations are combined with the environmental variations, we define design or process corners. The term corner refers to an imaginary box that surrounds the guaranteed performance of the circuits. The corners are specified with five letters describing the nMOS, pMOS, interconnect, power supply, and temperature,respectively. The letters are F, T, and S, for fast, typical, and slow.
Basic Nomenclature :
- NMOS can be slow, typical, fast (S, T, F).
- PMOS can be slow, typical, fast (S, T, F).
- Temperature can be hot, typical, cold (S, T, F).
- Vdd can be high, typical, low (F, T, S).
Example of Process corners and their detailed description. Process Corner Label may include NMOS, PMOS, Temp, Vdd.
- TTTT = typical NMOS, typical PMOS, room temp, nominal supply.
- SSSS = slow NMOS, slow PMOS, hot temp, low supply.
- FSSS = fast NMOS, slow PMOS, hot temp, low supply.
Sources of Process Variations:
(i) Lithographic variations : Uniformity of the printed feature sizes depends heavily on the control of the lithographic imaging system. A small vibration in the apparatus can lead to non-uniformity of the critical dimension (CD) of printed lines and significantly change the speed and leakage of CMOS transistors.
(ii) Line Edge roughness : It is the deviation in feature dimension from intended shape. Arises from variations in lithography and etching process.
(iii) Random Dopant Fluctuation : RDF refers to the random microscopic fluctuation of the number and location of dopant atoms in the MOSFET channel region. It causes fluctuations of the transistor electric parameters, such as the threshold voltage (Vt), short channel effect and drain-induced barrier lowering (DIBL).
(iv)Well proximity Effect : Advanced CMOS technology use high energy implants to form the deep retrograde well . During the implant process, atoms can scatter laterally from the edge of the photo-resist mask and become embedded in the silicon surface close to the well edge. As a result well surface concentration changes with lateral distance from the mask edge, over the range of 1um or more. Threshold voltages and other electrical characteristics also vary with the distance of the transistor to the well-edge. This phenomenon is known as the well proximity effect (WPE).
(v) STI & Length Of Diffusion : STI is forming trench and filling it is with nonconducting material to isolate active regions . This filling material exerts compressive stress to the vicinities, i.e., in diffusion areas. This stress is commonly referred as STI stress, also called Length of Diffusion (LOD) effect, where the characteristics of a device vary according to the distance of its gate from the diffusion edge. Mechanical stress change free carrier mobility. Consequently, transistors with the same gate size but a different LOD may have very different speeds. The stress increases as the channel to STI/Active edge distance decreases.
Impact of Process Variations:
The MOSFET parameters parameters are affected by relevant process steps. A single process step can affect multiple transistor parameters. Decoupling the effects of one variation source from another is extremely difficult.
(i) Carrier Mobility (μ) : Mobility is the ability of the carriers (electrons/holes) to travel through the channel of a MOSFET with an applied electric field. Mobility of carriers in the channel is impacted by doping concentration since the it determines the mean free time between collisions. The dose and energy of ion implantation and annealing temperature directly influence mobility since these process steps primarily determine doping concentrations. Strain engineering of a device channel, either by using local techniques such as Nitride liners and SiGe in source/drains, or global techniques such as SiGe substrates, affect the device mobility. Unintentional stresses induced due to STI can cause intra-die mobility variations of a few percent depending on the transistor distance to the STI edge.
(ii) Gate Oxide Capacitance (Cox) : Gate oxide, thicknesses are scaled to atomic level on the order of five atomic layers (10˚A). A small change in one atomic layer can greatly impact on not only the oxide capacitance, but also the threshold voltage and mobility of the MOSFET device. A small variation in the thickness of just one atomic layer would result in a 20% variation in the gate oxide thickness. Controlling this variation is difficult due to physical limitations at this atomic scale. Use of high-K dielectric material as gate oxide results in Moving to a new gate oxide material not only reduces gate leakage currents but also reduces the impact of variability on C ox due to the much larger physical oxide thickness. However, variations in the oxide of "high-k" stacks interfaces are still problematic and can also affect performance.
(iii) Threshold Voltage (Vth): Threshold Voltage is determined by the number and location of dopant atoms implanted in the channel or halo region. Ion implantation is a stochastic process, leading to random dopant fluctuations (RDF) that cause Vth to vary . Impact of statistical distribution become even more significant as device dimension The variations have become large in nanometer processes because the number of dopant atoms is small.
(iv) Transistor Dimensions (W , L) : The saturation current shows that the width and length of a transistor influence the device Current.
Processing steps and related factors like the wafer mask, exposure time, etching process, spacer definition, source/drain implantation and even the environment during the manufacturing process contribute to the overall variation in gate length and width. Any variation in channel length is directly reflected in device delay which is directly proportional to the channel length. Shrinking of the device channel length is physically limited by the patterning wave length ( λ=193 nm for 45 nm Technology node), therefore patterning a very short channel length below this wavelength becomes extremely difficult to control leading to an increase in gate length variation.
(vi) Yield (Y): In CMOS yield Y indicates the fraction of products that are operational. It is the probability that a particular product will work. So Failure probability is expressed as X = 1 – Y. Design techniques and analysis tools are used to minimize the range of variability. Variability more than permissible range cause failure and thus yield reduces. At each node, the dimensions get smaller and thus a constant variability actually means greater percentage of change. Small percentage of variability create larger impact in these dimension.
(vii) Delay: A change in ON current changes the delay of an inverter by the same fraction. An M-input gate will have up to M transistors that can vary separately. The delay of an N-stage path is the sum of the delays through each stage. If the variations are completely correlated , the delay of the path will have the same variance as the delay of a gate. However, if the variations are independent, the variance reduces by a factor of N × M.
(viii) Energy: Variation has a minor impact on dynamic energy. Variation has a major impact on static leakage energy. Static leakage energy is exponentially sensitive to threshold voltage. Systematic variation in Vt makes a tremendous impact because all transistors are correlated and the exponential has a long tail.
Analysis Methods for Studying Variability :
Digital circuits are designed in a way so that the circuits should meet the performance specifications such as speed and power consumption under all operating conditions. Statistical fluctuations in the semiconductor fabrication processes leads to undesirable circuit performance. It is necessary to model manufacturing process variations to predict the device and circuit performance to minimize the impact of parameter variation on the circuit performance and maximize the yield. There are different general techniques and methodologies used to handle the impact of process variations in circuit design such as,
i. Worst Case-corner Analysis
ii. Monte Carlo Analysis Technique
iii. Design of Experiments and Response Surface Modelling (DoE/RSM)
iv. Sensitivity Analysis
Modeling Variability :
Variations are modeled with : Uniform Distribution ; Gaussian Distribution.
Uniform distribution refers to a type of probability distribution in which all outcomes are equally likely. Uniform distributions are specified with half-range a.
Example : uniform distribution for VDD as 1.0 V ±10%. Here half range is 100.
Normal distribution also known as Gaussian distribution. A probability distribution that is symmetric about the mean, showing that data near the mean are more frequent in occurrence than data far from the mean. Normal distributions are specified with a standard deviation X . Processing variations are usually modeled with normal distributions.
Circuit designers commonly treat process variation as a combination of global variation and local variation. This method lumps all the chip-to-chip and wafer-to-wafer variations into one global variation component, and the remaining variations as one local variation component.
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