Clock GatingIn CMOS, Power Management-4

In this article, we delve into the intricate topic of clock gating in CMOS circuits, providing a comprehensive overview. We start by discussing the importance of power management and how clock gating plays a crucial role in reducing power consumption. The article compares clock-gated registers with non-clock-gated registers, highlighting the differences in performance and efficiency. We then explore various types of clock gating techniques, including AND-based, latch-based, flip flop-based, and MUX-based methods, along with bus-specific clock gating (BSCG) and its optimized version (OBCG). Further, we cover local explicit clock gating (LECG), enhanced clock gating (ECG), and typical clock gating circuits, emphasizing type and delay matching, multiple-stage implementations, and the overall advantages and challenges associated with clock gating.

Power Management & Clock Gating:

Clock gating, very effective in reducing the power consumption. This technique reduces power consumption by using a clock gater. Clock gater /turn off the clock that is driving a part of the logic when it's not required.  It will not affect the original functionality of the design.  The goal of this technique is to disable/suppress propagation of transitions to some parts of the clock path under certain condition.

Power savings happen due to :

(1) reduction in switching capacitance in the clock network

(2) reduction in switching activity in the logic fed by the storage elements since unnecessary transitions are not loaded when the clock is not active.

The clock signal is computed by function fcg. CLK is the system clock and CLKG the gated clock of the functional unit.

Automatic clock gating is supported by modern EDA tools. They identify the circuits where clock gating can be inserted.

There are many clock gating styles implemented to optimize power in VLSI circuits :  

(1) Latch-free based design,

(2) Latch-based design

Clock Gated vs. Non-Clock Gated Registers :

1. Non Clock gated Register :

2. Clock gated Register :

3. Non Clock Gating Ckt without Enable :

4. Non Clock Gating Ckt with Enable :

Different Types of Clock Gating :

Commonly used clock gating techniques:

1. AND Based Clock Gating

2. Latch Based Clock Gating

3. Flip Flop Based Clock Gating

4. MUX Based Clock Gating

Advanced clock gating schemes :

(A) Clock Gating Without Enable Signal :

1. Bus Specific Clock Gating (BSC)

2. Threshold based clock gating (TCG)

3. Optimized bus specific clock gating (OBSC)

(B) Clock Gating With Enable Signal

1. Local explicit clock gating (LECG)

2. Enhanced clock gating (ECG)

AND Based Clock Gating :

In AND gate based scheme the enable signal explicitly control the clock input to the logic block. Here if enable signal goes inactive between the clock pulse, clock output prematurely terminates(hazard problem). Or if En goes multiple times on and off between clock pulses then it generates multiple clock pulses. This restriction makes this circuit inappropriate.

Latch Based Clock Gating :

The latch based clock gating style adds a level- sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. The anomaly occurs when enable signal changes during the sleep period leading to an incorrect design. Here hazard problem that exits in AND gate design is removed but glitch problems is still there.

Flip Flop Based Clock Gating :

A similar technique to latch based design with one difference that instead of latch, D flip flop is used here. The same anomaly which existed in latch based design exists here too with longer sleep period. So the probability of missing the

change on the enable pin is high. Therefore this technique is not used much. Also area overhead increases much in comparison to latch based technique.

MUX Based Clock Gating :

In this technique the feedback path is controlled by the mux. Mux is controlled by select line when it is required to close or open the feedback path. This circuit is simple robust and often a reasonable choice. But this circuit uses one fairly expensive mux per bit and consume more power.

Bus Specific Clock Gating (BSCG) :

BSCG is used to reduce the dynamic power and it can be realized using D-flip-flops, AND, XOR and OR gates.

BSCG circuit compares the inputs and outputs and gates the clock when they are equal. When there is change in the input data of gated FFs then only the gated clock is applying for D-FFs otherwise the gated clock signal is not applying. Power consumption will be high if output toggle rate increases which indicates high switching activity of the signal.

Threshold Based Clock Gating (TCG) is another data driven clock gating technique. In this technique toggle rates of FFs of non-clock gating circuit need to be tested at first time, and then according to the list of toggle rate, those FFs are divided into two parts. In this way disadvantages of BSC technique is removed.

Optimized Bus-Specific Clock Gating (OBCG) :

This is a fine grained and activity-driven CG methodology.  The FFs are clustered based on relationship between them. The problem of gated FF selection is reduced from exponential complexity into linear. It works by comparing the inputs and outputs and gates the clock when they are equal.

Local Explicit Clock Gating (LECG) :

Here clock of Flip flop is gated explicitly by using enable signal. This enable signal increase the control of the circuit explicitly.  Here as long as EN=0 no clock is passed of flipflop and hence no power consumption, but power consumption starts when en is high i.e 1. If en=1 period is significantly high than over all power consumption increase due to additional circuitry which over weighs the savings.

Enhanced Clock Gating (ECG):

This method combines both BSCG and LECG and make use of the advantages of both methods. In BSCG switching activity increase the power dissipation which is eliminated by using EN signal which gated the circuit for that much period of time. If the mentioned situation is not emerged then this method consume more power because of complex circuit

than previous to methods.

Typical Clock Gating Circuit:

Clock gating can reduce the power consumed by flipflops and the clock distribution network.  A groups of flip-flops are identified and clock port of each FF connected with

the O/P of clock gating circuit.  A common enable signal is used to control the clock gating circuit .  Therefore, if a group of flipflops which share a common enable term have clock gating implemented, the flip- flopswill consume zero dynamic power as long as this enable term is false. 

There are two technique to implement

clock ­gating:

(1) Type matching

(2) Delay matching

Type Matching Clock Gating :

In type-matching clock gating same logic gates are used in same levels.

Delay Matching Clock Gating :

In delay matching clock gating cells with same timing requirements are used.

Multiple Stage Clock Gating:

Multi-stage clock gating style exists, where the clock gating is cascaded. The clock signal of the first stage clock gating (CG Stage 1) is gated by the second stage clock gating (CG Stage 2). The gated clock signal should arrive at CG Stage 1 earlier than the enable signals EN_A, EN_B and EN_C to maintain the functional correctness of the circuit. That is if EN_A, EN_B and EN_C depend on the outputs of other flip- flops in the circuit, the minimum delay of enablesignals EN_A, EN_B and EN_C should be larger than the gated clock.

Advantages & Challenges of Clock Gating :

(1) Dynamic power reduction :  In clock gating, clock signal does not reach idle parts of the circuit. Power is saved as switching activity minimized.

(2) Reduced Heat generation : Since switching is less, power

consumption reduces. As a result heat generation reduces.

(3) Enhanced Battery Life : For battery powered movable devices like smartphones and laptops, clock gating is very useful. Since power dissipation reduces , battery life increases.

Challenges of Clock Gating :

(1) Timing Violations : Introduction of gating logic may lead to setup and hold time violations.

(2) Synchronization Issue : Since the clock is enabled and disabled in various parts , that might lead to synchronization problem.

(3) Delay : Introduction of extra logic of clock gating may introduce clock path.

Watch the video lecture here:

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