In this article, we have comprehensively discussed power gating in CMOS circuits, providing a detailed overview of its principles and applications. We began by exploring power management strategies, focusing on how power gating can be effectively implemented in System on Chip (SoC) designs. Key topics included the retention strategy, various circuit configurations, and critical power gating parameters. We differentiated between global and local power gating, delving into specific techniques like switch-in cell gating and the distinctions between fine and coarse grain power gating. Additionally, we examined different implementation styles, such as ring and column style, and discussed the figures of merit that evaluate the effectiveness of power gating in circuit designs.
Power Management & Power Gating :
The basic idea of power management arise from the fact that all parts of a circuit are not needed to function all the time. The power management scheme can identify conditions under which either certain parts of the circuit or the entire circuit can remain idle and shut them down to reduce power consumption. One of the technique to reduce the leakage power. In this technique a MOSFET switch or sleep transistor is used to cut off/gate, a circuit from the power rails (Vdd and/or gnd) during standby mode. The switch typically is positioned as header between the circuit and the Vdd or as footer between the circuit and the ground. Power gating has 2 modes : Sleep/Stand By mode & Active mode. During active operation, the power gating switch remains on, supplying the current that the circuit uses to operate. During standby mode, turning off the power gating switch reduces the current dissipated through the circuit.
Power Gated SoC :
There are three major components of a power gated SoC.
Power Switches : A power switch is a PMOS/NMOS transistor that disconnects the circuit from the power supply, ground, or both power and ground networks, when power gating is engaged.
Isolation Cells : Isolation Cell is placed between power gated block and the active/always ON block. During Power Gating operation, the circuit will contain few ON and OFF domains together at any point of time. In such situation, output of a OFF domain sends invalid signal to the ON Domain. To deal with such problematic situation Isolation Cell is placed.
Controller : Controllers are used in standard power gating applications to control and synchronize local power switches and isolation cells with clock gating or power gating signals.
Retention Strategy :
A retention strategy is required otherwise all state information is lost when the block is powered down. To resume its operation on power up, the block must either have its state restored from an external source or build up its state from the reset condition. In either case, the time and power required can be significant. One of the following three approaches may be used:
(1) Software Approach : In the software approach, the always-ON CPU reads the registers of the power-gated blocks and stores in the processor’s memory. During power-up sequence, the CPU writes back the registers from the memory.
(2) Scan-based Approach : Scan-Based Approach Scan chains used for built-in self-test (BIST) can be reused. During power-down sequence, the scan register outputs are routed to an on-chip or off-chip memory. In this approach, there can be significant saving of chip area.
(3) Register-based Approach : Standard registers are replaced by retention registers, that contains a shadow register which can preserve the registers state during power down and restore it at power up.
Circuit Configuration :
(1) Sleep Technique :
(2) Zig-zag Method :
(3) Sleepy Stack Method :
Power Gating Parameters :
Power Gate Size : The power gate size is selected to handle the amount of switching current at any given time. The gate must be bigger such that there is no measurable voltage (IR) drop due to the gate. As a rule of thumb, the gate size is selected to be around 3 times the switching capacitance. Designers can also choose between header (P-MOS) or footer (N-MOS) gate. Usually footer gates tend to be smaller in area for the same switching current. Dynamic power analysis tools can accurately measure the switching current and also predict the size for the power gate.
Gate Control Slew Rate : In power gating, this is an important parameter that determines the power gating efficiency. When the slew rate is large, it takes more time to switch off and switch-on the circuit and hence can affect the power gating efficiency. Slew rate is controlled through buffering the gate control signal.
Simultaneous Switching Capacitance : This important constraint refers to the amount of circuit that can be switched simultaneously without affecting the power network integrity. If a large amount of the circuit is switched simultaneously, the resulting “rush current” can compromise the power network integrity. The circuit needs to be switched in stages in order to prevent this.
Power Gate Leakage : Since power gates are made of active transistors, leakage reduction is an important consideration to maximize power savings.
Power-Gating Topologies :
1. Global Power Gating :
Global power gating refers to a logical topology in which multiple switches are connected to one or more blocks of logic, and a single virtual ground is shared in common among all the power-gated logic blocks. This topology is effective for large blocks (coarse- grained) in which all the logic is power gated, but is less effective, for physical design reasons when the logic blocks are small. It does not apply when there are many different power-gated blocks, each controlled by a different sleep enable signal.
2. Local Power Gating :
Local power gating refers to a logical topology in which each switch singularly gates its own virtual ground connected to its own group of logic. This arrangement results in multiple segmented virtual grounds for a single sleep domain.
3. Switch in Cell Gating :
Switch in cell may be thought of as an extreme form of local power-gating implementation. In this topology, each logic cell contains its own switch transistor. Its primary advantages are that delay calculation is very straightforward. The area overhead is substantial in this approach.
Power-Gating Granularity :
1. Fine Grain Power Gating:
The power-gating switch is placed locally as part of the standard cell. As a result the size of the switch is usually large and there is significant area overhead. All cell had VGND port . All cells in a domain share same VGND port.
2. Coarse Grain Power Gating:
A relatively larger block or a block of gates is power switched by a block of switch cells. IP Core is surrounded by VGND. Switch is between VGND and GND
Power-Gating Implimentation :
1. Ring Style Implementation :
Switches are placed external to the power-gated block by encapsulating it by a ring of switches. Switches connect VDD to the virtual VVDD of the power-gated block. This is the only style that can be used to supply power to an existing hard block by placing the switches outside it.
2. Grid Style Implementation :
The switch cells are added as multiple columns within the logic block. Here the global power grid inside the block is routed in the higher metal layers, while the switched power rails are routed in lower layers.
Figures Of Merit For Power-Gating
Performance Degradation (α): A design/input specification that defines the maximum allowable delay increase in the design/logic block. Increase in the original critical path delay permitted when the design/logic block is power-gated. This parameter is denoted by α, expressed as the percentage increase in the original critical path delay.
Sleep Transistor Size (Wsleep): Sleep transistor size depends mainly on two parameters: (i) The virtual ground voltage, VVGN D ; (ii) The peak discharge current of the design/logic block, Ipeak . For a given peak current value Ipeak, one can have a lower VVGND value to obtain a lower speed degradation of the cells in the power- gated design, thus resulting in a larger sleep transistor. On the other hand, a higher value of VVGND would lead to a smaller sleep transistor, but to a higher delay degradation of the cells in the power-gated design.
Leakage Power Savings: The main benifit of power-gating is how much leakage power can be saved.
Power Mode Transition Time (PMt): In a power-gated design/block, the turn-off time is the time required by the design/block to go from the active to the stand-by mode, and the turn-on time as the time required by the design/block to make the opposite mode transition.
Power-mode transition energy (PMe): This quantity denotes a non-negligible energy dissipation during turn-on/off of the sleep transistor. The energy loss occurs in the charging and discharging of the virtual ground line capacitance and in the buffers which drive the sleep transistor. This parameter is strongly coupled with the size of the sleep transistor.
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