Clock Tree Synthesis in VLSI

This article covers a broad range of topics related to clock tree synthesis (CTS) in VLSI design flow. The discussion begins with an introduction to CTS and its significance in VLSI design, followed by an overview of pre- and post-CTS diagrams. The various levels involved in the CTS process and the CTS methodology are also explained, along with the role of CTS in EDA tools.

Clock distribution and routing is important in digital design as it impacts Power, Performance and Area (a.k.a PPA) of the SOC design. The Clock Tree Synthesis (CTS) process impacts maximum operating clock frequency through the clock skew. Process Variation generated race-around conditions are avoided through CTS. In test mode, many flip-flops are hooked together to form a scan chain. The skew requirements of scan-chain are stringent for the scan clock tree as every path during test mode is a short  path. The clock tree network is responsible for a significant amount of power dissipation as it switches most frequently. Clock trees are good candidates for low power VLSI designs.

CTS in VLSI Design Flow:

Now lets see exactly where in the VLSI flow CLOCK Tree Synthesis is done. First take a look at the VLSI Design Flow. 

From above flow we can understand that CTS is done in between Placement and Routing. 

Clock Tree Synthesis :

Clock spine routing scheme with all clock pins driven directly from the clock driver. FPGAs often use this fish bone type of clock distribution scheme. A clock spine for a gate array.

A clock spine for a cell-based ASIC. Typical chips have thousands of clock nets. A clock spine is usually driven from one or more clock-driver cells. Delay in the driver cell is a function of the number of stages and the ratio of output to input capacitance for each stage (taper). Clock latency and clock skew. An Engineer tends to minimize both latency

and skew.

Pre & Post CTS : 

There is a clock root and without CTS clock signal goes to each end leaf cells or FlipFlops directly from clock root. After CTS there are number of buffers inserted so that proper power management could be done.  

Various Levels During CTS:

Above diagram shows various levels of the clock network during CTS. Synthesizing required intermediate buffers are the basic objective of CTS process.  

CTS Methodology:

In order to reduce iterations & TAT , clock tree designs methodologies are developed by engineers. This can consist of sub steps : design of the tree structure, layouting the clock tree and synchronization of multiple trees of the same clock source. 

In details the steps can be :

1. Generate Netlist with Specific Number of Receivers in              Clock Tree.

2. Design the tree structure from bottom up process.

3. Use the layout tool features to form the clock tree.

4. Through analysis of delay and skews for all clock nets.

5. Iterate with correction until target is achieved.

CTS In EDA Tool:

EDA toold are used for CTS. Clock Specification File is used. Spec generation option is also available there.

Above diagram shows EDA tool GUI.

Watch the video lecture here:

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