VHDL/System Verilog in UPF. Episode : 4 ~ TechSimplifiedTV.in

In this article, we cover several important aspects related to UPF and HDL simulation. We start by discussing the integration of UPF with HDL simulation, highlighting the synergy between these two critical components in power management. Next, we explore the different categories and syntax of UPF functions, providing a detailed explanation of how they operate and their significance. The article also addresses UPF supply query functions, shedding light on their role in managing power supply information. Additionally, we delve into the concepts of supply nets and data types within HDL, explaining how they interact and contribute to efficient power management. We introduce the Switching Activity Interchange Format (S.A.I.F), which is essential for analyzing power consumption. Lastly, we discuss the System-Verilog and VHDL packages for UPF, illustrating how these packages facilitate the integration of UPF into various design environments and enhance simulation capabilities.

UPF & HDL Simulation:

The voltage value and full/partial state of a supply net are valid only when its on/off state is asserted. Every time the state or voltage value of the power or ground nets changes, the power of the corresponding design elements is evaluated.

If both power and ground supply nets are on, the design element instances connected to the given supply pair are turned on. If power or ground supply net is off, the power to the design element instances is turned off. In turned off state every sequential element and every signal driven from within the powered-down element is called corrupted. Events that were scheduled before the power was turned off and whose target is inside a powered down instance shall have no effect.

UPF Functions:

UPF Functions Syntax :

UPF Supply Query Functions :

This is the verification side of UPF. Here we will see the functions that can do query to the designs.

get_supply_value : it will get the supply value

get_supply_voltage : it will get the supply voltage

get_supply_on_stage : it will check the on stage

get_supply_state : it will get the supply state

These are the UPF query functions that are required in verification.

Supply Net Data Types in HDL:

SystemVerilog:

typedef struct packed {

int voltage;// voltage in μV

bit [31:0] state;// net state

} supply_net_type;

VHDL:

type supply_net_type is record

voltage : numeric_bit.signed(31 downto 0);// voltage in μV

state : bit_vector(31 downto 0); // net state

end record;

subtype net_state is bit_vector(1 downto 0);// the defined state bits

Supply Net in UPF:

The create_supply_net command provides an option that specifies the type of resolution to be used by the supply net.

The following resolution methods shall be provided:

Unresolved : The supply net may only be connected to a single output (this is the default).

One Hot : Multiple outputs may be connected to the supply net. At most,one of the outputs may be ON at any particular time.

Parallel : Multiple outputs may be connected to the supply net.

Switching Activity Interchange Format S.A.I.F:

SAIF stands for Switching Activity Interchange Format. It is designed to assist in the extraction and storing of the switching activity information generated by EDA tools. A SAIF file containing switching activity information can be generated using an HDL simulator. This switching activity can be back-annotated into the power analysis/optimization tool.

SystemVerilog Package for UPF :