What Is Standard Cell Characterization?

 

This article provides a comprehensive guide to Standard Cell Characterization in VLSI design for beginners. The discussion begins with a concise overview of Standard Cell Characterization and highlights how Standard Cells are the building blocks of ASIC (Application-Specific Integrated Circuit) design. Then it moves on to explain the Standard Cell Design Flow and delves deeper into the concept of Handcrafted CMOS Layout. The types of cells present inside the library and variations in cell design, such as VT, Track, and Drive Strength, are also explored. The Front-End View Generation and Back-End View Generation processes are explained, along with the creation of Liberty files. The article also provides an overview of what happens in Characterization and the concept of a cell .lib Library (Liberty). Finally, a summary is provided, outlining the key points covered in the discussion.

Standard Cells : Building Block of ASIC

Standard cells are the building blocks of ASIC designs. We can understand this with a simple analogy shown in above figure of Lego blocks kids loves to play with. A  chip is built with different types of IPS and majority of them are standard cell IPs.

Standard Cell Libraries are required by all tools used in the ASIC Design RTL-to- GDS flow. It contains primitive cells as well as complex cells too. Standard Cells are designed by Variation of Power-Performance-Area (PPA). For each cell a variety of drive strengths are present. Inverters and Buffers have much Larger drive strengths varieties than any outer cells. Cells contains balanced rise and fall delays. Cell with delay variation present to aid fixing of STA violations. Standard Cell heights(dimensions) are denoted by Track. Variation may be 7T , 11T etc. The distance between two consecutive tracks is called the Pitch.

Standard Cell Design Flow:

This is the design flow of standard cell. The flow starts with specification/requirement. It includes all the information which is necessary for the standard cell. After that either schematic or RTL design is done. Schematic is for analog standard cell and RTL design is for digital standard cell. Next we do the CDL or RTL simulation to get the electrical characteristics. The SPICE-OUT step is for schematic or CDL to get the spice netlist. After that HSPICE/Spectre/Eldo simulation is done on spice netlist. 

After frontend, backend flow starts and layout is drawn using Virtuoso. Then we do DRC/LVS , RC Extraction and Physical verification. In Physical Verification we go for antenna checks , EM checks etc. Once all these checks are done we can move to characterization and standard cell delivery.

Handcrafted CMOS Layout :

For PMOS there is N-well and P -select whereas for NMOS there is N-select. Inside N and P select  diffusion layers and Source and Drain contacts are created as shown above. Before creating contacts all the steps involved are in FEOL. After that Poly gates are created and connected with each other see Fig 4b. At final steps  Vdd, GND and Vout connections are created see Fig 4c. Connection between transistors , Source or  Drain contact creation and Poly gate creation and connection all are included in MEOL. Any step  beyond output contact creation is included in BEOL.

Types of Cells Inside The Library:

A standard cell library usually have Basic logic gates such as AND/OR/NAND, Half adder/Full adder, Multiplexer, ECO cells (specially used for ECO or Electronic Change Order), Tie Cells, AOI/AND-OR Inverter, OAI/ OR-AND Inverter, Flip flops, Scan Flops, Latches, Filler Cells, Tap Cells, End Cap Cells, D -Cap Cells, Clock cells.

Cell Design Variation : VT

Threshold voltage is varied in standard cell design. Ultra low Vt, Low Vt, Standard Vt, High Vt and Ultra High Vt are some Vt variations.

Cell Design Variation : Track

Track or height is another parameters that is varied in standard cells. According to ascending order of cell  12.5T> 10.5T> 9T, 7.5T, 6T. More the track number the height of the cell is higher and area of the cell is bigger.  

 

Cell Design Variation : Drive Strength

Drive strength or drivability of a cell is the third parameter to vary. Drivability means how many output a particular standard cell can drive. 

Front-End View Generation : 

Some front end views available in standard cell library are RTL views like Verilog, VHDL,  SystemVerilog, DB, SDB, SLDB,UPF,CPF,OA etc. 

Back-End View Generation : 

Layout views, Mapping File, NDM, GDSII, LEF, DEF, DB OASIS, CIF, Abstract View are some backend views present in standard cell distribution. Physical verification related views and tool related views could be there.

How Liberty File is Created ?

Liberty file is used in timing analysis. standard cell library is passed through the .lib characterization process and finally we get a ASCII file with .lib extension. This file is in liberty format.

What Happens in Characterization?

We have our basic gates and our netlist which are passed on to characterization engine.  There is a TCL config file which contains all setup info and list of runs need to take place. Then the engione is connected to LSF/UGE, these are load sharing facility runs with token assigned to teams. Since these runs requires lot of memories , high memory machines are used and LSF knows which one to select. Its a setup abvailable in companies and system people takes care of it. Engineers just need to understand how to properly use it. From LSF the whole process launches multiple spice simulation and cumulative result comes back.After that we proceed towards model generation. NLDM, CCS, ECSM, OCV are some common model that is generated. All these data are put in the ASCII format in .lib file. 

Cell .lib Library (Liberty):

Timing Engine Reads a set of Cell Library files (.lib).The .lib file is a text file containing timing and power parameters  associated with any standard cell for a given technology node. It contain the data for all standard cells available to the design in the specified technology node. So , each instance in the verilog/vhdl/systemverilog netlist must have a corresponding cell found in the .lib library. The .lib file contains pre-characterized timing models and data to calculate I/O Delay paths , Timing Check Values & Interconnect Delays,To compensate the PVT and OCV variation de-rating factors are also included.

Summary :

Standard Cell Library is a collection of Basic as Well As Advanced Cells. Standard Cells will contain Consolidated Timing Library (.lib) for all the cells . This is the major product of the Characterization. One particular cell will have multiple views and variations based on parameters like Track/VT/Drive Strength. Standard Cells are the biggest IP collection by volume among all Foundation IPs. Hence its characterization is also cumbersome and time consuming. Without the Characterized Standard Cell Library the Digital VLSI SOC Design is impossible !

Watch the video lecture here:

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