Design Flow and Pin Assignment :
When planning the layout of large blocks, where you place the connection points (terminals) is very important. These connection points, called I/O pins, are usually placed on the edges of the blocks to keep the wiring short. The best spots for these pins depend on how the blocks are arranged. During pin assignment, each signal (net) is assigned a specific pin location to improve the overall design. The main goals are to make sure the wiring is easy to route and to reduce unwanted electrical effects both inside and outside the block. The objective of external pin assignment is to link each incoming or outgoing signal to a unique I/O pin. After assigning each necessary net to its designated pin, the connections must be optimized to minimize wire length and reduce electrical parasitics, such as coupling or signal integrity loss.
More on Pin Assignment :
Pin assignment is used to connect cell pins that are functionally or electrically equivalent, such as during standard cell placement. Two pins are considered functionally equivalent if swapping them does not alter the design's logic, and they are electrically equivalent or equi-potential if they are connected. The primary goal of internal pin assignment for cells is to minimize congestion and reduce interconnect length between cells. The pin assignment techniques described below are applicable to both chip planning and placement stages.
Pin Assignment using Concentric Circles :
The algorithm connect a block to all its associated pins in other blocks with minimum of cross-connections. It operates under the assumption that all outer pins have fixed positions. Inner pins are positioned based on the locations of their electrically equivalent outer pins. The algorithm employs two concentric circles: the inner circle for the pins of the block being considered and the outer circle for pins in other blocks. The primary goal is to assign valid pin locations on both circles w/o no net overlap.
1. Determine the Circles :
The two circles are drawn such a way that all pins that belong to the block are outside the inner circle and all external pins are outside the outer circle.
2. Determine the Points :
For each point, draw a line from that point to the center of the circles. Then, move each outer point to where the line meets the outer circle, and move each inner point to where the line meets the inner circle.
3. Determine Initial Mapping :
The initial setup pairs each outer pin with a matching inner pin. Start by choosing any pin and assign it to an inner pin. Then, assign the rest of the pins either in a clockwise or anti-clockwise direction.
4. Optimizing the Mapping :
Repeat the process of pairing outer and inner points in different ways. Start with the same outer point, but try pairing it with different inner points, and then pair the rest of the points accordingly. Continue until all possible pairings have been tried. The best pairing is the one that has the shortest total distance between the points. In this problem, an example pairing is shown on the left, the best pairing is in the center, and the final pin assignments are on the right.
Topological Pin Assignment :
This algorithm is an improvement to concentric-circle pin assignment algorithm. It takes into account external block positions and multi -pin nets. This allowed pin assignment even when external pins are behind other blocks. This algorithm is an improvement to concentric-circle pin assignment algorithm. It takes into account external block positions and multi -pin nets. This allowed pin assignment even when external pins are behind other blocks.
This method allows multiple block to be considered simultaneously. There are two blocs a & b. On block a, consider the midpoint lines lm~a and lm~b. The point d1 is formed because it is the farther point on lm~a. The point d2 is formed because it is closer point on lm~b. The point d3 is formed because it is the farther oint on lm~b. Using d1-d3, the pins are “unwrapped” accordingly when projected onto m’s outer circle.
Design Flow : Power & Ground Routing :
Chip planning involves designing the power-ground distribution network and positioning supply I/O pads or bumps. Up to 20-40% of all metal resources on the chip are used to supply power (VDD) and ground (GND) nets.
The power planning process includes iterative steps such as:
1. Early simulation of major power dissipation components.
2. Initial estimation of overall chip power.
3. Analysis of total chip power and peak power density.
4. Examination of total chip power fluctuations.
5. Analysis of inherent and additional fluctuations caused by clock gating.
6. Early analysis of power distribution, including average, maximum, and multi-cycle fluctuations.
Design of a Power-Ground Distribution :
Every cell needs both VDD and GND connections. They connect each cell in the design to a power source. VDD and GND supply lines are large, cover the entire chip, and are routed before any signal lines. Core supply lines differ from I/O supply lines, which usually have a higher voltage. Single core power line and core ground line are often enough, For some ICs, like mixed-signal or low-power designs, may have multiple power and ground lines. Routing power/ground lines is different from routing signal lines. Power/ground lines require their own metal layers to avoid taking up space needed for signal routing. Thicker metal layers, typically the top two in the manufacturing process, are preferred for power and ground lines due to their lower resistance. When the power-ground network spans multiple layers, sufficient vias must be used to carry current and prevent reliability issues like electro-migration. Supply lines carry high current, so they are often much wider than signal lines. The width of each wire segment can be adjusted based on the expected current. Wider segments have lower resistance, which reduces voltage drop.
There are two main approaches to designing power-ground distribution:
1. The planar approach : used in analog or custom blocks.
2. The mesh approach : more common in digital ICs.
Planar Routing:
Power supply nets can be routed using planar routing when
(1) only two supply nets are present in the design,
(2) a cell needs a connection to both supply nets.
A Hamiltonian path is created that connects all the cells. The path divides the layout into two regions: one for each supply net. Each supply net is routed either the left/right side of the path for each cell. So both supply nets can be laid out without conflicts in across the design.
Routing the power and grounds nets and grounds nets in this planar fashion can be accomplished with the following three steps:
1. Planarize the topology of nets:
Since both power and ground nets must be routed on the same layer, the design should be divided using a Hamiltonian path. Start routing the power and ground nets from the left and right sides, respectively. Ensure both nets expand in a tree-like structure, avoiding overlap and maintaining separation by the Hamiltonian path. The precise routing will depend on the pin locations. Connect the cells wherever a pin is encountered during the routing process.
2. Layer Assignment :
3. Determining the widths of the net segment:
Mesh Routing :
Power-Ground routing in state-of-art IC has mesh topology. There are five steps followed to create the topology.
1. Creating a Ring :
A ring is built around the main part of the chip, and sometimes around specific sections. The ring's job is to link the power supply and any electrostatic discharge protection to the chip's overall power network. To keep resistance low, these connections, as well as the ring, are spread across multiple layers of metal. For instance, the ring might use metal layers from Metal2 to Metal8, skipping only Metal1.
2. Connecting I/O pads to the ring :
The top figure shows the connectors from the I/O pads to the ring. Each I/O pad has several metal layers with multiple fingers extending from it. These fingers should be connected as much as possible to the power ring to reduce resistance and improve the flow of current to the core.
3. Creating a Mesh :
A power mesh is made up of a series of stripes placed at specific intervals across two or more layers. The width and spacing of these stripes are determined by estimated power consumption and layout design rules. The stripes are arranged in alternating pairs, such as VDD-GND, VDD-GND, and so forth. The power mesh primarily uses the uppermost and thickest layers, while the lower layers have fewer stripes to prevent signal routing congestion. Stripes on neighboring layers are typically connected with as many vias as possible to reduce resistance.
4. Creating Metal1 rails :
The Metal1 layer is where the power-ground distribution network connects to the design's logic gates. The width and spacing (current supply capability) of the Metal1 rails are usually defined by the standard cell library. The standard cell rows are arranged "back to back," allowing each power supply net to be shared between two adjacent cell rows.
5. Connecting the Metal1 rails to the mesh :
Finally, the Metal1 rails are connected to the power mesh using stacked vias. A critical factor is ensuring the appropriate size of the via stack (i.e., the number of vias in the stack). Ideally, the most resistive part of the power distribution should be the Metal1 segments between the via stacks, rather than the stacks themselves. Additionally, the via stack is optimized to preserve the design's routing flexibility. For instance, depending on the direction of routing congestion, a 1x4 array of vias might be more effective than a 2x2 array.
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