This article comprehensively covers several key points relating to Yosys and GH-Clone. First, it provides a thorough introduction to GH-Clone, elucidating its functionality and guiding viewers through the installation process. Following this, it demonstrates the practical application of GH-Clone by showcasing how to copy Yosys CMOS test cases using this tool. Moreover, the article highlights the execution of Synthesis flow test cases, showcasing a hands-on approach by running and comparing these test cases side by side in two distinct terminals. Finally, it delves into a detailed comparison between the outputs of the two different test cases, providing insights into the nuances and variations between them. Through these discussions and demonstrations, viewers gain a comprehensive understanding of utilizing GH-Clone, executing test cases, and analyzing their outputs within the context of Yosys synthesis.
Revisiting the Test Case with a New Approach :
We’ll start with the same test case used in the last episode but access it differently this time. Using the `gh clone` tool, we’ll download the test case directly from the GitHub repository. If you haven’t installed `gh clone` yet, don’t worry—we’ve got you covered.
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Websites as shown In video lecture:
JSON format on WikiPedia : https://en.wikipedia.org/wiki/JSON
NetlistSVG : https://neilturley.dev/netlistsvg/
Graph VIZ in Yosys : https://yosyshq.net/yosys/screenshots.html
Install Yosys & GraphViz in Ubuntu Linux :
sudo apt-get update -y
sudo apt-get install -y yosys
sudo apt-get install -y graphviz
dot -V
sudo apt-get instakk tkdiff
GH Clone And Installation:
URL : https://github.com/HR/github-clone
sudo apt-get install pip pipsi
sudo apt-get install python3
sudo pip install github-clone or : sudo pipsi install github-clone
CMOS TestCase:
https://github.com/YosysHQ/yosys/tree/main/examples/cmos
Setting Up the Test Environment:
After downloading the test case, we’ll create two directories: tc1 and tc2. In each directory, we’ll execute different synthesis methods on the same test case:
1. tc1: Use a high-level synthesis macro (`synth`) to automate the process.
2. tc2: Perform synthesis using detailed step-by-step commands.
Step-by-Step Synthesis vs. High-Level Macro:
Here’s how the synthesis process unfolds:
Using `gh clone`, we’ll clone the required test case into both directories.
bash gh clone "GitHub-URL-to-test-case"
This creates a directory with the necessary files, ready for synthesis.
2. Launching Yosys:
In each directory, we’ll start Yosys and begin the synthesis process.
3. tc1: Using the Macro Command:
A single `synth` command executes multiple synthesis steps:
- Reading Verilog files.
- Optimizing hierarchical structures.
- Mapping RTL and cell libraries.
- Performing logic synthesis.
4. tc2: Using Baby Steps:
Instead of a single macro, we execute each step manually:
read_verilog: Parses the design into an internal format.
proc: Converts behavioral Verilog into muxes and flip-flops.
opt: Optimizes and cleans up intermediate files.
fsm: Analyzes and optimizes state machines.
techmap: Maps coarse-grained cells to fine-grained logic cells.
- Additional steps for optimization and mapping to library cells.
Each step mirrors the functionality bundled within the `synth` macro, providing deeper insight into the synthesis process.
Comparing Results:
Once synthesis is complete, we generate and compare the output netlists using tkdiff. This allows us to examine:
- Behavioral Verilog vs. synthesized netlist differences.
- Netlist consistency between macro-based and stepwise synthesis methods.
Conclusion: Which Method is Better?
Both methods yield identical synthesized netlists, confirming that the synth macro internally performs the same steps as manual synthesis. However, using the macro is more efficient for most scenarios, while the step-by-step approach is ideal for learning and debugging.
Stay tuned for more deep dives into Yosys workflows! 🚀
Watch the video lecture here:
Courtesy: Image by www.pngegg.com
