In this article, we delve into several critical topics related to the synthesis process and verification in VLSI design. We begin by discussing pre-synthesis checks and the standard verification methodology, emphasizing the importance of these steps in ensuring a robust design. Next, we explore synthesizable HDL constructs, highlighting the specific coding practices that enable efficient synthesis. We then examine the role of the standard cell library in synthesis, explaining how these pre-characterized cells facilitate the design process. We provide an overview of the generic internal process steps of synthesis, detailing what happens during synthesis and illustrating these stages with informative infographics that depict both the initial and final stages of logic synthesis. Additionally, we discuss two types of optimizations in Yosys, a popular open-source synthesis tool, and explain the constant folding algorithm, which is crucial for optimizing the design by evaluating constant expressions at compile time.
Pre-Synthesis Checks :
1. Functional Design Verification:
-Confirm the design's functional accuracy
- Follow a verification methodology.
2. Verification Approach:
- Create a verification plan based on the design spec
- Develop test-benches for simulation.
3. Verification Steps:
-Instantiate the Design Under Test (DUT) to test.
- Apply input stimuli to the DUT.
- Verify the DUT's output against expected results.
4. Testbench Execution:
-Utilize HDL simulators for testbench execution
- For Verilog: Choose from icarus verilog or verilator
- For VHDL: Opt for GHDL for simulation.
Standard Verification Methodology :
1. Directed Tests:
- Prepare input stimuli (test vectors) manually.
- Detects bugs based on known issues.
2. Constrained Random Verification:
- Randomize input stimuli with specific constraints.
- Uncertainty about which functions are tested.
3. Coverage:
- Measures testing comprehensiveness.
- Includes code coverage and functional coverage.
4. Universal Verification Methodology (UVM):
- SystemVerilog-based class library.
- Highly powerful but intricate.
- Contains over 300 classes.
- Limited familiarity for graduate students new to SystemVerilog.
5. Open Source VHDL Verification Methodology (OSVVM):
- VHDL-based library - Resembles UVM in concept
Synthesizable HDL Constructs :
Synthesizable Verilog/VHDL:
- Designed for hardware description and synthesis to physical circuits.
- Uses hardware constructs like flip-flops, logic gates, and multiplexers.
- Focuses on sequential and combinational logic.
- Timing is critical; designs must meet setup and hold time requirements.
- Typically follows specific coding guidelines for synthesis compatibility.
- Emphasizes efficient resource utilization and timing closure.
- Suitable for implementing designs on FPGA or ASIC hardware.
Non-Synthesizable Verilog/VHDL:
- Used for modeling behavior and simulation purposes.
- Can include constructs that don't directly map to hardware, like delays and tasks.
- Focuses on functionality and ease of simulation.
- Timing considerations might be less critical or not relevant.
- Offers more flexibility in coding style and language features.
- Used for test benches, simulation of functional behavior, and algorithmic modeling.
- Not guaranteed to produce functional hardware when directly synthesized.
Standard Cell Library & Synthesis:
Synthesis requires attaching a technology library, making it essential to understand the standard cell library. Here are key episodes to enhance your knowledge:
- A crucial episode from the STA series that explains timing library contents, electrically characterized data, and how to retrieve cell-specific information.
Synthesis Internal Process Steps :
This flowchart outlines the internal process of any synthesis tool, starting with the HDL description (e.g., Verilog or VHDL) and progressing through key steps. Note that this is not the full VLSI design flow but rather a generic representation of synthesis. While the process may vary between EDA tools, the core steps are similar.
1. HDL Translation:
- The HDL description is translated into an unoptimized intermediate representation.
2. Logic Optimization:
- Synthesis tools apply optimization algorithms to improve PPA (Power, Performance, Area) for the target design.
3. Technology Mapping and Optimization:
- Includes design constraints to ensure the synthesis stays within specified boundaries.
- Incorporates a technology-specific standard cell library for mapping.
- The choice of standard cells is influenced by variations like high-Vt, low-Vt, fast/slow processes, and PVT (Process, Voltage, Temperature) variations.
For a deeper understanding, watch related episodes covering PVT and RC corner variations, as well as PPA optimization, linked in the video description.
4. Optimized Gate-Level Netlist:
- The final output is an optimized, technology-specific gate-level netlist, ready for the next stage of the design flow.
Synthesis connects the generic design (written in HDL) to a specific technology node by integrating the library and constraints. This process marks the beginning of technology-specific implementation.
What Happens During Synthesis :
Two-Level Boolean Minimization:
- Crucial for optimization.
- Targets finite state machines for improvement.
- Aims to reduce product terms and their sizes for a more compact and faster implementation.
- Seeks to find an equivalent FSM with fewer states.
- Advisable to reduce the problem size before technology mapping and technology-dependent optimizations.
Automatic Synthesis of Logic Implementation:
- Involves several steps:
- HDL synthesis programs process the code.
- These programs infer logic and state elements.
- Technology-independent optimizations are performed, including logic simplification and state assignment.
- Elements are mapped to the target technology.
- Technology-dependent optimizations are applied, such as multi-level logic optimization.
Logic Synthesis : Initial & Final Stages
Logic synthesis, the initial and the final stages. In this slide, we will explain using infographics and we will point out the things that we have said during the last flowchart we have explained. Here, the table contains 3 columns. 1st column is named as equation, so here we'll have the Boolean equation. Next, we have the initial intermediate netlist and sometimes this is called the initial netlist or the intermediate netlist also.
And here, we will show you the final optimized netlist. Sometimes it is called the final netlist and sometimes it is called the optimized netlist also. These names can have variants from either taking partial name from these 2 or from these 2. And so you must be very careful and hence, we have included all the possible words here. And we'll have 2 different rows.
That means we'll be talking about 2 different equations. So the first equation is this is a Boolean equation. You can see z equals to a and b and which we are ordering with c. How the netlist will look? So there will be then this netlist.
So there is a ending b and all is or to c. So this is c is or to the a and b. And there's a very simple thing that we can draw by hand. So this will be done by the synthesis tool as a initial netlist. However, as it further goes down and goes through optimization, it will transform it for the technology optimized one.
So here you can see the NAND gates are there. These are the gates which require less spaces. Obviously, this netlist can be in a different form and shape as per the kind of technology optimization that you are doing. As part of the library, as part of the PPA and the PVD and RC corner, all those things. Obviously, RC will not come here because it's a front end.
However, for the process corners and all those things, they will be there. And they will be residing inside the standard cell library. That's why I have just uttered these terms. Next equation is z is equal to del then question mark then a or b. So this is a ternary operator, you know, from Verilog language.
Or even this ternary operator is there in the c language also. However, this gives out a mux, which is a 2 to 1 mux where c is the selecting. So, generally, this is the initial net list that will be generated by the synthesis tool After a set of optimization and including the technology optimization, it might result bucket like this, where we have either the feed optimized or the area optimized gates. So these are the technology gates that are from the standard cell library. So all those things will be there.
Or it might happen the standard cell has different variants of this particular mux in it, and the required mux will be picked up by the synthesis tool. That can also happen. These are not hard coded things and these are set of infographics for understanding. I am not hard coding that this will happen or that will happen. I am not predicting that.
So you have to be very careful when you are running this kind of optimization and you will see that what kind of optimization is done and what is the initial, what is the final netlist. Here we are done through the infographics for the initial and the final stages of the optimization or a circuit. And this is just an example. The actual case may have different form and shapes of, initial and the final net list. We are done talking about this.
So let's move on to the next slide. Two types of optimization. Here, basically, we will talk about 2 different types of optimization that we do in Eosys as a synthesis tool. 1st, there are optimizations. The first type of optimization, initial or non recursive, that means they will be only at the beginning and they will optimize once.
And there are some of the optimization that are recursive. That means, these will repeat until a stable result is achieved. So these are optimization algorithms. Some of them will run one time and some of them will run multiple time. EOC's optimization passes.
EOC offers optimization passes for HDL synthesis including the opt pass, which performs various simple optimizations. These optimizations involve removing unused signals and cells and constant folding. This is another algorithm that we will be talking in the next slide. It's recommended to run the opt pass after significant synthesis script steps for better results. So this is an algorithm that we can include more than one time.
The opt pass comprises multiple individual passes. So this is basically a macro, and that will contain multiple optimization processes. Each of the substeps focusing on specific simple optimization task. So once you run the opt routine, it will run small small steps. That is the beauty of having a synthesis tool where there are some macros which contains some couple of set of optimization that will run once you execute that particular optimization.
And it is called optimization. It is not called a macro. Macro is a generic term that we are using. A macro is a set of commands are tied together. That is the definition of a macro.
And in VLSI, you will find another macro which is called a macro cell. We are clarifying it right away.
Two Types of Optimizations:
Yosys Optimization Passes:
Yosys offers optimization passes for HDL synthesis, including: The "opt" pass, which performs various simple optimizations. These optimizations involve removing unused signals and cells, and constant folding. It's recommended to run the "opt" pass after significant synthesis script steps for better results. The "opt" pass comprises multiple individual passes, each focusing on specific simple optimization tasks.
Constant Folding Algorithm :
The "opt_expr" pass in Yosys focuses on constant folding for internal combinational cell types. It replaces cells with all constant inputs with the constant value they drive, and sometimes optimizes cells with some constant inputs. Replacement rules for optimizing $_AND_ gates are defined, including const folding and propagation of undef (X) states. Undef states are allowed to propagate only in specific cases, as per IEEE Std. 1364-2005. In cases where no other substitutions are possible in the module, the pass assumes the value 0 for undef states. $_AND_ gates with a constant-1 input can be replaced with a buffer. Additionally, 1-bit wide $eq and $ne cells with one constant input can be replaced with buffers or not-gates. The "opt_expr" pass is cautious when optimizing $mux cells to avoid interfering with decision-tree modeling and other optimizations.
