LVS in VLSI Physical Design with NETGEN: Episode- 3

 

In this article, we walk through three practical examples using NETGEN to tackle common Layout versus Schematic (LVS) issues in VLSI design. We start with a simple introduction to the topic and explain a buffer circuit, which we use in our example spice file. We also compare SPICE files obtained from schematic and the other one extracted from layout and highlight why LVS tools are essential. By exploring common problems like missing global definitions and mismatched device counts, we provide step-by-step guidance on troubleshooting. Finally, we break down the NETGEN output log file to help you confidently identify and fix LVS errors.

Basic of buffer circuit:

This is a buffer circuit. It is comprised of 2 inverter. If Vin = 0/1 after 2 inversion Vou =0/1 .So voltage level there will be no change. And the single inverter is comprised of 2 MOSFET. One is pFET, another one is nFET. So pFET and nFET, their width and length are mentioned 1.8 micron, 0.6 micron respectively, width and length. So this is the buffer circuit that data we will use in the spice files. Now let's compare 2 spice files.

Comparison of .spice files:

# bufferA.spice : Generated from a layout in Magic. Starts numbering transistors from 1000(That is the convention).   Includes details about transistor area and perimeter for more accurate simulation. Lists device width, length, area and perimeter details.

# bufferB.spice : Created with a schematic capture too/written manually. Uses the non-standard keyword .backanno. Pin order for the "inverter" subcircuit differs frombufferA.spice. Lists device width and length but lacks area and perimeter details.

With our plane eyes , if we try to compare, we will find many differences between two spice files although they represent same circuit. This is the scenario in a very small and simple circuit. And now just think, if the circuit is really big and complex, it's impossible to compare them with eyes. That's why we need tool. An LVS tool is important for that.

Run & Explanation of 1st Example:

We will run LVS with NETGEN for files bufferA.spice and bufferB.spice along with an empty setupfile.tcl

# Command :  netgen lvs bufferA.spice bufferB.spice setup.tcl lvs_run.out

The output file mentions about the mismatch in device properties mentioned across spice files although finally the circuits match uniquely  as both the spice file  represent same circuit.

Run & explanation of 2nd Example:

Now in 2nd example we will make a change in bufferB.spice file  and save it as bufferBx.spice. In bufferBx .spice file we have commented or omitted the global definition and run it with empty setupfile. 

Now netlist does not match.

 

Now we will use a new setupfile and will run LVS again.The setup file contains:

After using the setupfile circuits match.

The Global pin definition which os missing in bufferBx.spice  file is provided using the setupfile. SO finally the circuits matches.

Run & explanation of 3rd Example:

Now let's run another example where  there are mismatch in device number between two spice files.

We will run LVS on these two spice files.

As we can see the run time output saying Netlists do not match.

Output log is reporting about mismatch in number of devices across .spice files.

This is the final report. Now since the number of devices are more in the schematic  netlist, we need to check the schematic file to correct it.

Watch the video here:

Courtesy: Image by www.pngegg.com