In this article, we delve into the intricate topic of clock gating in CMOS circuits, providing a comprehensive overview. We start by discussing the importance of power management and how clock gating plays a crucial role in reducing power consumption. The article compares clock-gated registers with non-clock-gated registers, highlighting the differences in performance and efficiency. We then explore various types of clock gating techniques, including AND-based, latch-based, flip flop-based, and MUX-based methods, along with bus-specific clock gating (BSCG) and its optimized version (OBCG). Further, we cover local explicit clock gating (LECG), enhanced clock gating (ECG), and typical clock gating circuits, emphasizing type and delay matching, multiple-stage implementations, and the overall advantages and challenges associated with clock gating.
Power Management & Clock Gating:
Clock gating, very effective in reducing the power consumption. This technique reduces power consumption by using a clock gater. Clock gater /turn off the clock that is driving a part of the logic when it's not required. It will not affect the original functionality of the design. The goal of this technique is to disable/suppress propagation of transitions to some parts of the clock path under certain condition.
Power savings happen due to :
(1) reduction in switching capacitance in the clock network
(2) reduction in switching activity in the logic fed by the storage elements since unnecessary transitions are not loaded when the clock is not active.
The clock signal is computed by function fcg. CLK is the system clock and CLKG the gated clock of the functional unit.
Automatic clock gating is supported by modern EDA tools. They identify the circuits where clock gating can be inserted.
There are many clock gating styles implemented to optimize power in VLSI circuits :
(1) Latch-free based design,
(2) Latch-based design
Clock Gated vs. Non-Clock Gated Registers :
1. Non Clock gated Register :
2. Clock gated Register :
3. Non Clock Gating Ckt without Enable :
4. Non Clock Gating Ckt with Enable :
Different Types of Clock Gating :
Commonly used clock gating techniques:
1. AND Based Clock Gating
2. Latch Based Clock Gating
3. Flip Flop Based Clock Gating
4. MUX Based Clock Gating
Advanced clock gating schemes :
(A) Clock Gating Without Enable Signal :
1. Bus Specific Clock Gating (BSC)
2. Threshold based clock gating (TCG)
3. Optimized bus specific clock gating (OBSC)
(B) Clock Gating With Enable Signal
1. Local explicit clock gating (LECG)
2. Enhanced clock gating (ECG)
AND Based Clock Gating :
In AND gate based scheme the enable signal explicitly control the clock input to the logic block. Here if enable signal goes inactive between the clock pulse, clock output prematurely terminates(hazard problem). Or if En goes multiple times on and off between clock pulses then it generates multiple clock pulses. This restriction makes this circuit inappropriate.
Latch Based Clock Gating :
The latch based clock gating style adds a level- sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. The anomaly occurs when enable signal changes during the sleep period leading to an incorrect design. Here hazard problem that exits in AND gate design is removed but glitch problems is still there.
Flip Flop Based Clock Gating :
A similar technique to latch based design with one difference that instead of latch, D flip flop is used here. The same anomaly which existed in latch based design exists here too with longer sleep period. So the probability of missing the
change on the enable pin is high. Therefore this technique is not used much. Also area overhead increases much in comparison to latch based technique.
MUX Based Clock Gating :
In this technique the feedback path is controlled by the mux. Mux is controlled by select line when it is required to close or open the feedback path. This circuit is simple robust and often a reasonable choice. But this circuit uses one fairly expensive mux per bit and consume more power.
Bus Specific Clock Gating (BSCG) :
BSCG is used to reduce the dynamic power and it can be realized using D-flip-flops, AND, XOR and OR gates.
BSCG circuit compares the inputs and outputs and gates the clock when they are equal. When there is change in the input data of gated FFs then only the gated clock is applying for D-FFs otherwise the gated clock signal is not applying. Power consumption will be high if output toggle rate increases which indicates high switching activity of the signal.
Threshold Based Clock Gating (TCG) is another data driven clock gating technique. In this technique toggle rates of FFs of non-clock gating circuit need to be tested at first time, and then according to the list of toggle rate, those FFs are divided into two parts. In this way disadvantages of BSC technique is removed.
Optimized Bus-Specific Clock Gating (OBCG) :
This is a fine grained and activity-driven CG methodology. The FFs are clustered based on relationship between them. The problem of gated FF selection is reduced from exponential complexity into linear. It works by comparing the inputs and outputs and gates the clock when they are equal.
Local Explicit Clock Gating (LECG) :
Here clock of Flip flop is gated explicitly by using enable signal. This enable signal increase the control of the circuit explicitly. Here as long as EN=0 no clock is passed of flipflop and hence no power consumption, but power consumption starts when en is high i.e 1. If en=1 period is significantly high than over all power consumption increase due to additional circuitry which over weighs the savings.
Enhanced Clock Gating (ECG):
This method combines both BSCG and LECG and make use of the advantages of both methods. In BSCG switching activity increase the power dissipation which is eliminated by using EN signal which gated the circuit for that much period of time. If the mentioned situation is not emerged then this method consume more power because of complex circuit
than previous to methods.
Typical Clock Gating Circuit:
Clock gating can reduce the power consumed by flipflops and the clock distribution network. A groups of flip-flops are identified and clock port of each FF connected with
the O/P of clock gating circuit. A common enable signal is used to control the clock gating circuit . Therefore, if a group of flipflops which share a common enable term have clock gating implemented, the flip- flopswill consume zero dynamic power as long as this enable term is false.
There are two technique to implement
clock gating:
(1) Type matching
(2) Delay matching
Type Matching Clock Gating :
In type-matching clock gating same logic gates are used in same levels.
Delay Matching Clock Gating :
In delay matching clock gating cells with same timing requirements are used.
Multiple Stage Clock Gating:
Multi-stage clock gating style exists, where the clock gating is cascaded. The clock signal of the first stage clock gating (CG Stage 1) is gated by the second stage clock gating (CG Stage 2). The gated clock signal should arrive at CG Stage 1 earlier than the enable signals EN_A, EN_B and EN_C to maintain the functional correctness of the circuit. That is if EN_A, EN_B and EN_C depend on the outputs of other flip- flops in the circuit, the minimum delay of enablesignals EN_A, EN_B and EN_C should be larger than the gated clock.
Advantages & Challenges of Clock Gating :
(1) Dynamic power reduction : In clock gating, clock signal does not reach idle parts of the circuit. Power is saved as switching activity minimized.
(2) Reduced Heat generation : Since switching is less, power
consumption reduces. As a result heat generation reduces.
(3) Enhanced Battery Life : For battery powered movable devices like smartphones and laptops, clock gating is very useful. Since power dissipation reduces , battery life increases.
Challenges of Clock Gating :
(1) Timing Violations : Introduction of gating logic may lead to setup and hold time violations.
(2) Synchronization Issue : Since the clock is enabled and disabled in various parts , that might lead to synchronization problem.
(3) Delay : Introduction of extra logic of clock gating may introduce clock path.
In this article, we have comprehensively discussed power gating in CMOS circuits, providing a detailed overview of its principles and applications. We began by exploring power management strategies, focusing on how power gating can be effectively implemented in System on Chip (SoC) designs. Key topics included the retention strategy, various circuit configurations, and critical power gating parameters. We differentiated between global and local power gating, delving into specific techniques like switch-in cell gating and the distinctions between fine and coarse grain power gating. Additionally, we examined different implementation styles, such as ring and column style, and discussed the figures of merit that evaluate the effectiveness of power gating in circuit designs.
Power Management & Power Gating :
The basic idea of power management arise from the fact that all parts of a circuit are not needed to function all the time. The power management scheme can identify conditions under which either certain parts of the circuit or the entire circuit can remain idle and shut them down to reduce power consumption. One of the technique to reduce the leakage power. In this technique a MOSFET switch or sleep transistor is used to cut off/gate, a circuit from the power rails (Vdd and/or gnd) during standby mode. The switch typically is positioned as header between the circuit and the Vdd or as footer between the circuit and the ground. Power gating has 2 modes : Sleep/Stand By mode & Active mode. During active operation, the power gating switch remains on, supplying the current that the circuit uses to operate. During standby mode, turning off the power gating switch reduces the current dissipated through the circuit.
Power Gated SoC :
There are three major components of a power gated SoC.
Power Switches : A power switch is a PMOS/NMOS transistor that disconnects the circuit from the power supply, ground, or both power and ground networks, when power gating is engaged.
Isolation Cells : Isolation Cell is placed between power gated block and the active/always ON block. During Power Gating operation, the circuit will contain few ON and OFF domains together at any point of time. In such situation, output of a OFF domain sends invalid signal to the ON Domain. To deal with such problematic situation Isolation Cell is placed.
Controller : Controllers are used in standard power gating applications to control and synchronize local power switches and isolation cells with clock gating or power gating signals.
Retention Strategy :
A retention strategy is required otherwise all state information is lost when the block is powered down. To resume its operation on power up, the block must either have its state restored from an external source or build up its state from the reset condition. In either case, the time and power required can be significant. One of the following three approaches may be used:
(1) Software Approach : In the software approach, the always-ON CPU reads the registers of the power-gated blocks and stores in the processor’s memory. During power-up sequence, the CPU writes back the registers from the memory.
(2) Scan-based Approach : Scan-Based Approach Scan chains used for built-in self-test (BIST) can be reused. During power-down sequence, the scan register outputs are routed to an on-chip or off-chip memory. In this approach, there can be significant saving of chip area.
(3) Register-based Approach : Standard registers are replaced by retention registers, that contains a shadow register which can preserve the registers state during power down and restore it at power up.
Circuit Configuration :
(1) Sleep Technique :
(2) Zig-zag Method :
(3) Sleepy Stack Method :
(4) Dual-Sleep Method :
(5) Dual Stack Method :
Power Gating Parameters :
Power Gate Size :The power gate size is selected to handle the amount of switching current at any given time. The gate must be bigger such that there is no measurable voltage (IR) drop due to the gate. As a rule of thumb, the gate size is selected to be around 3 times the switching capacitance. Designers can also choose between header (P-MOS) or footer (N-MOS) gate. Usually footer gates tend to be smaller in area for the same switching current. Dynamic power analysis tools can accurately measure the switching current and also predict the size for the power gate.
Gate Control Slew Rate : In power gating, this is an important parameter that determines the power gating efficiency. When the slew rate is large, it takes more time to switch off and switch-on the circuit and hence can affect the power gating efficiency. Slew rate is controlled through buffering the gate control signal.
Simultaneous Switching Capacitance :This important constraint refers to the amount of circuit that can be switched simultaneously without affecting the power network integrity. If a large amount of the circuit is switched simultaneously, the resulting “rush current” can compromise the power network integrity. The circuit needs to be switched in stages in order to prevent this.
Power Gate Leakage :Since power gates are made of active transistors, leakage reduction is an important consideration to maximize power savings.
Power-Gating Topologies :
1. Global Power Gating :
Global power gating refers to a logical topology in which multiple switches are connected to one or more blocks of logic, and a single virtual ground is shared in common among all the power-gated logic blocks. This topology is effective for large blocks (coarse- grained) in which all the logic is power gated, but is less effective, for physical design reasons when the logic blocks are small. It does not apply when there are many different power-gated blocks, each controlled by a different sleep enable signal.
2. Local Power Gating :
Local power gating refers to a logical topology in which each switch singularly gates its own virtual ground connected to its own group of logic. This arrangement results in multiple segmented virtual grounds for a single sleep domain.
3. Switch in Cell Gating :
Switch in cell may be thought of as an extreme form of local power-gating implementation. In this topology, each logic cell contains its own switch transistor. Its primary advantages are that delay calculation is very straightforward. The area overhead is substantial in this approach.
Power-Gating Granularity :
1. Fine Grain Power Gating:
The power-gating switch is placed locally as part of the standard cell. As a result the size of the switch is usually large and there is significant area overhead. All cell had VGND port . All cells in a domain share same VGND port.
2. Coarse Grain Power Gating:
A relatively larger block or a block of gates is power switched by a block of switch cells. IP Core is surrounded by VGND. Switch is between VGND and GND
Power-Gating Implimentation :
1. Ring Style Implementation :
Switches are placed external to the power-gated block by encapsulating it by a ring of switches. Switches connect VDD to the virtual VVDD of the power-gated block. This is the only style that can be used to supply power to an existing hard block by placing the switches outside it.
2. Grid Style Implementation :
The switch cells are added as multiple columns within the logic block. Here the global power grid inside the block is routed in the higher metal layers, while the switched power rails are routed in lower layers.
Figures Of Merit For Power-Gating
Performance Degradation (α): A design/input specification that defines the maximum allowable delay increase in the design/logic block. Increase in the original critical path delay permitted when the design/logic block is power-gated. This parameter is denoted by α, expressed as the percentage increase in the original critical path delay.
Sleep Transistor Size (Wsleep): Sleep transistor size depends mainly on two parameters: (i) The virtual ground voltage, VVGN D ; (ii) The peak discharge current of the design/logic block, Ipeak . For a given peak current value Ipeak, one can have a lower VVGND value to obtain a lower speed degradation of the cells in the power- gated design, thus resulting in a larger sleep transistor. On the other hand, a higher value of VVGND would lead to a smaller sleep transistor, but to a higher delay degradation of the cells in the power-gated design.
Leakage Power Savings: The main benifit of power-gating is how much leakage power can be saved.
Power Mode Transition Time (PMt): In a power-gated design/block, the turn-off time is the time required by the design/block to go from the active to the stand-by mode, and the turn-on time as the time required by the design/block to make the opposite mode transition.
Power-mode transition energy (PMe): This quantity denotes a non-negligible energy dissipation during turn-on/off of the sleep transistor. The energy loss occurs in the charging and discharging of the virtual ground line capacitance and in the buffers which drive the sleep transistor. This parameter is strongly coupled with the size of the sleep transistor.
The article delves into crucial aspects of power optimization in CMOS circuits. In this atricle, we have explored various strategies for optimizing power in electronic circuits comprehensively. We started with an overview of power optimization circuits, touching on key low power design methodologies and examining the extensive power reduction design space. We delved into the concept of power states, discussing techniques such as voltage scaling, multi-voltage scaling, and power gating, which are crucial for reducing power consumption. Further, we covered clock tree optimization and clock gating, as well as advanced transistor techniques like dual, multi, and variable threshold MOSFETs and transistor stacking. The discussion also included the use of special cells for power optimization, interconnect strategies, and the tools available for implementing these power optimization techniques.
Low Power Design Methodologies :
Whatever power goes inside the IC comes out as heat. Continues current flow in the circuit increases junction temperature and that heat must be dissipated. That dissipation happens through the packaging. Power optimization in IC is a must otherwise the heat dissipation If the chip Packaging and its costs, Power supply rail design,
- Chip and system cooling costs
- Noise immunity and system reliability
- Battery life (in portable systems)
In VLSI design circuit speed has been considered as performance metric. Power considerations has become ultimate design criteria in portable applications. Aim of these applications is to maximize battery life time, with minimum power. LPD also need to reduce the power in high-end systems with huge integration density and thus improve the speed of operation. Digital systems design is spread over multiple steps from system to process level. To optimize power (specifically for LPD), the method should be applied over all steps. It is very important to have knowledge about the power distribution. So the blocks or parts consuming fraction of power could be clearly optimized for saving power.
Power Reduction Design Space :
1. Power reduction through system integration :
- Utilize low system clocks
- Use high level of integration
- Integrating off-chip memories (ROM, RAM, etc.) and other ICs such as digital and analog peripherals.
2. Power reduction by algorithm level :
- Minimizing the number of operation. That reduces the number of H/W resources
- Data coding for reduce the switching activity.
3. Power reduction through architectural model :
- Power management by shutting down unused blocks
- Low-power architectures based on parallelism, pipelining, etc.
- Memory partition with selectively enabled blocks
- Reduction of the number of global busses
- Minimization of instruction set for simple decoding and execution.
4. Power reduction through circuit/logic design :
- Reduce switching activity by optimized algorithm
- Optimize clock and bus loading
- Circuit techniques which minimizes number of devices used in the circuit
- Custom design may improve the power
- Reduces VDD in non-critical paths and proper transistor sizing
- Use of multi-VT circuits
5. Power reduction through process technology :
- One way to reduce the power dissipation is to reduce the power supply voltage. Reduction in Vdd increases delay. To match the device with supply voltage scaling is the option.
- The advantages of scaling for LPD are : improved current drive capabilities,
reduced capacitances through small geometries and junction capacitances
- Improved interconnect technology
- Availability of multiple and variable threshold devices
- This results In good management of active and standby power trade-off
- Higher density of integration.
What are Power States :
An IP performs certain functional jobs. It is designed for that. Since power is the concern for state-of-art appliances we must optimize power for IP operations. To optimize and save power we must understand the usage of any IP first . We can define different operation modes for an IP and accordingly necessary power would differ. Thus operations modes of an IP are also termed as power states.
Depending on functional role of an IP, Power states are defined and power is saved. Power states are defined and differentiated from each other based on corresponding functional mode. Based on usage power is reduced and saved. In some cases, power states can have sub-states.
Voltage Scaling :
Supply Voltage Scaling :
Used to reduce dynamic and leakage power. Lowers subthreshold current and gate leakage current. The optimal point for power savings using this technique is the lowest voltage which the circuit retains its logic states and does not compromise performance. To achieve low-power benefits without compromising performance, two ways of lowering supply voltage can be employed: the static supply scaling and the dynamic supply scaling.
Static Supply Scaling: ( Voltage Islands)
Multiple supply voltages are used as per operation requirement. Critical and non-critical paths and/or units re clustered and powered accordingly. Whenever an output from a low Vdd unit has to drive an input of a high Vdd unit, a level conversion is required at the interface.
Dynamic Supply Scaling :
This technique uses single supply voltage. Hence cost is less. When performance demand is low, supply voltage and clock frequency are lowered. Substantial power reduction is possible by that. Circuit need to be operable over a wide voltage range. Operating system to intelligently determine the processor speed. Regulator to generate the minimum voltage for specific speed.
Multi Voltage Scaling :
Dynamic Voltage and Frequency Scaling (DVFS):
A larger number of voltage levels are dynamically switched to follow changing workloads.
Adaptive Voltage Scaling (AVS):
An extension of DVFS where a control loop is used to adjust the voltage.
Multi-Voltage Design Challenges :
1. Level shifters:Signals that go between blocks that use different power rails require level shifters.
2. Characterization and STA:Need libraries for each voltage and level shifter configuration.
3. Floorplanning: Complex power planning and power grids
4. Board level issues: Need additional regulators to provide the additional supplies.
5. Power up and power down sequencing: There may be a required sequence for powering up the design.
Power Gating :
One of the technique to reduce the leakage power. In this technique a MOSFET switch or sleep transistor is used to cut off/gate, a circuit from the power rails (Vdd and/or gnd) during standby mode. The switch typically is positioned as header between the circuit and the Vdd or as footer between the circuit and the ground. Power gating has the basic strategy of providing Sleep/Stand By mode & Active mode. During active operation, the power gating switch remains on, supplying the current that the circuit uses to operate. During standby mode, turning off the power gating switch reduces the current dissipated through the circuit.
Clock Tree Optimization & Clock Gating :
Clock signal is the most fundamental signal for any digital circuit and Clock signal consumes the most amount of the total power. The design of clock network is important in order to make the low power system achieve good functional stability under low voltage. Clock distribution is crucial for timing and design convergence. Most of the power is consumed due to the high clock frequency used for operating the device. Up to 70% or even more of the dynamic power can be spent in the clock buffers. This is a critical problem in every synchronous circuit. Portions of the clock tree that are not being used at any particular time can be disabled to save the power. This is clock gating and its an effective way of reducing the dynamic power dissipation.
One of the ways to achieve this is by masking the clock that goes to the idle portion of the circuit. Clock gating is particularly useful for registers that need to maintain the same logic values over many clock cycles. The main challenges of clock gating are finding the best places to use it and creating the logic to shut off and turn on the clock at the proper times.
Dual/Multi/Variable Vth MOSFET :
The present-day process technology allows the fabrication of MOSFETs of multiple Vt on a single chip. Dual-Vt CMOS circuits is used for high-performance and low-power CMOS circuits. High-Vt transistors used to reduce leakage current and low-Vt transistors to achieve high performance. There are various fabrication technique for implementing multiple Vt MOSFETs in a single chip.
1. Multiple Channel Doping : Commonly used technique for realizing multiple-VT MOSFETs is to use different channel doping densities
2. Multiple Oxide CMOS : Vth has a dependence on the value of Cox. Different Cox can be realized by using different Tox and accordingly Vth will be different.
3. Multiple Channel Length : Vth decreases as the channel length is reduced, known as Vth roll-off. This phenomenon is exploited to realize transistors of dual threshold voltages.
4. Multiple Body Bias : When the substrate and the source has a voltage difference that leads to an increase or decrease of the threshold voltage.
Multi-Threshold CMOS (MTCMOS) is a popular power gating approach that uses high Vth devices for power switches . Variable threshold CMOS is a body biasing based design technique.
Transistor Stacking :
Subthreshold leakage current flowing through a stack of series connected transistors reduces when more than one transistor in the stack is turned off. This effect is known as “stacking effect”. Consider a two transistor stack. When both M1 and M2 are turned off, the voltage at the intermediate node (Vx) is positive due to a small drain current.
Positive potential at the intermediate node has three effects:
1. Due to the positive source potential Vx, gate-to-source voltage of transistor M1 (Vgs1) becomes negative; hence, the subthreshold current reduces substantially.
2. Due to Vx > 0, bulk-to-source potential (Vbs1) of transistor M1 becomes negative, increasing the threshold voltage (Vth) (larger body effect) of M1, and thus reducing the subthreshold leakage.
3. Due to Vx > 0, the drain-to-source potential (Vds1) of transistor M1 decreases,increasing Vth (less DIBL) of M1, and thus reducing the subthreshold leakage. The leakage of a two-transistor stack less than the leakage in a single transistor.
Special Cells & Power Optimization :
1. Retention Cell :
Memories or registers are not capable of keeping their information while powered off. When a particular power domain inside chip is switched off, it is bound to loose its memory. To save such scenarios special retention cells have been adopted in most of the commercial standard cell libraries (eg. TMSC, UMC, GF), to support the State retention power-gating (SRPG). Retention cells store the last state before power off of a flop inside the power domain. Thus it allows the system to continue its operation from the last known state and faster wake up of a block. The only Drawback is the Retention Mode consumes little more current than power off mode.
2. Isolation Cell :
Inter-domain signals can become complicated if the connecting interface changes during different power modes. During Power Gating operation, the circuit will contain few ON and OFF domains together at any point of time. In such situation, output of a OFF domain sends invalid signal to the ON Domain. To deal with such problematic situation Isolation Cell is placed between power gated block and the active block. An Isolation Cell clamps the signal at its input pin to a defined known state, either logic "0 ‟ or logic "1". Hence transmission of invalid signal is eradicated.
3. Level Shifters Cell :
In multi voltage/power domain system, the logic gates on noncritical paths are operated with low VDD and gates on critical path are operated with high VDD. Chip with different supply voltage domains use level shifters to convert and propagate logic signals among different power domains.
4. Always On cells :
An "always on" cell in VLSI is designed to always remain powered on and active, regardless of the state of other cells or the input signals to the chip. These cells are typically used to provide critical functions that must be maintained even when the rest of the chip is in a low- power or sleep mo de, such as maintaining a clock or managing power domains.Such cells are carefully designed to minimize their power consumption while still providing the required functionality. Such Cells are like normal buffers with an extra secondary always-on pin to keep the cells ‘on’ even when primary power is off in a domain. This will remain ‘on’ through the secondary backup supply pin, which supplies the necessary current when the main supply is not available.
Interconnect & Power Optimization :
Interconnect-power reduction : A circuit consumes switching power Pswitch when the interconnection capacitances are charged and discharged. The interconnect power occupied more than half of the total dynamic power consumption Pdynamic ,with 90% of it contributed from 10% of the interconnections. To reduce Cdyn , larger wire spacing and minimal length routing were implemented for the high-power consuming interconnects.
Net ordering and wire space optimization :To optimize power consumption, interconnect capacitance must be reduced. That can be achieved by rearranging the wire positions I.e net ordering and wire space optimization. Signals with high switching activity (SA) share a relatively larger space than those with lower SA .
Tools & Power Optimization :
Commercial EDA tools effectively support power management techniques. They also provide additional power savings during implementation. Low power VLSI designs can be achieved at various levels of the design abstraction from algorithmic and system levels down to layout and circuit levels. Varieties of power analysis tools are available to estimate the power of a design. All commercial tool vendor have such tools. The power products are tools that comprise a complete methodology for low power design. Such tool offers power analysis and optimization from RTL to the gate level. Some tool provides transistor-level power analysis. Activity/switching rate are the basis of analysis for some power tools. In traditional flow each tool has their own low power design commands although there core description might be inconsistent. UPF is used in all tools for obtaining consistent low power consumption design requirements. Tools can be automatically inserted according to UPF description during FE integration. MTCMOS is inserted and connected in rear-end realization tools. Complex power connection, control signal connection are automatically realized according to UPF description. The operation is simple and convenient with high accuracy.
