Power Domains & Power Modes : UPF Episode - 5

In this enlightening episode, we delve into a series of intriguing topics that shed light on the fascinating realm of power domains and power modes in VLSI (Very Large Scale Integration). Inspired by a question posed by Sandeep Vasireddy during the inaugural episode of the UPF (Unified Power Format) in VLSI Series, we embark on a comprehensive exploration of power modes. Through a meticulous analysis, we unravel the concept of power modes, including their definition and significance in VLSI design. We also delve into the realm of popular power modes, exploring various examples and their applications within the industry. Furthermore, we delve into the intricacies of power domains, examining their fundamental nature and the criticality of power-up and power-down sequencing in VLSI systems. By the end of this episode, viewers will have gained a solid understanding of power modes and power domains, enabling them to apply this knowledge effectively in their own VLSI designs.

What is Power Mode ?

Power management is a feature that resides in modern electronic circuits residing inside copiers, laptop, Smart Phones, CPUs, GPUs, monitor , printer, that turns off the power partially or as a whole when inactive. Sleep mode is a low power mode for electronic devices. These modes save significantly on electrical consumption compared to leaving a device fully on.  Sleep mode also known by various names, including Stand By, Suspend and Suspend to RAM. Power mode names may vary from one IC/IP to another IC/IP. For any Specific IC , please consult the Data-Sheet to understand its power modes & its corresponding operations. To know the power-modes of any IP, you must contact the IP-Vendor for the respective Application Note on the available Power-Modes.

Popular Power Modes:

1. Idle Mode:

   -Stopped: CPU, Flash memory

   -Running: Comparator, ADC , Watchdog-Module

   -Wakeup:  External and internal interrupts

2. Power-Down Mode:

   -Stopped: All major & minor powered blocks

   -Running: External interrupts, Watchdog-Module

   -Wakeup: Watchdog-Module, External Interrupt

3. Standby Mode:

    -Running: External Crystal Clock Oscillator

   -Wakeup: Watchdog-module, external interrupt , up time is       higher than power-down mode

What is Power Domain ?

1. Power-Up & Power-Down Sequence : 

The power up sequence is the sequence in which the power is tuned on for the entire chip. The power down sequence is the sequence in which the power is shut down of the entire chip. This includes specifications of the time intervals between several steps in the mentioned sequence(s). A power sequence is used when there are Semiconductor Devices with different power supply voltages (a.k.a Power Domains) mixed together on one board/chip. The time interval specifications differ depending on the device, which can cause problems when applying power to on-board devices with different power supplies. In a general power sequence, power to the main block is applied first, followed by the peripheral blocks. The reverse occurs for power shutdown.

Summary:

Power-Modes Manages the power supply of various Power-Domains. According to a Specific Power-Mode , the Power Management Block Distributes Power to the Various Power Domains. Power Mode - is a Specification of POWERING/DE-POWRING Operation. Power Domain - is a Circuit Block with Specific Power Need.

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Digital-Buffer vs Logic Level Shifter: UPF Episode - 6

This episode of the UPF in VLSI Series aims to answer the question posed by one of our viewer in the third episode. The episode covers a range of topics, beginning with an introduction to digital buffers and the different types available. The concept of a level shifter, also known as a translator, is then explored, including the various types available. Viewers are then provided with a comparison of buffers and level shifters, including an example to help illustrate the differences between the two. The episode concludes with a summary of the key differences between the two components, with a focus on the SN74LV1T34 logic level shifter.

What is a Digital Buffer ?

A digital buffer a.k.a. voltage buffer, provides either "no voltage" or "a output voltage that is same as the input voltage". It draws very little current and will not disturb the original circuitry. To do this, a voltage buffer is constituted with a very high input impedance. As a consequence , the power source will not be affected. It is also called a unity gain buffer because it provides a gain of 1 hence serving no amplification factor. A Digital Buffer is widely used for Registers. A typical Digital Buffer that is used to control multiple data inputs written onto a bus is a Tri-State Digital Buffer, which controls the data flow by "tri- state" pins. 

Types of Digital Buffers:

Inverting Buffer : This kind of buffer produces the state opposite to the input. If the input is high, the output is low and vice versa. Graphically, it is often represented as a triangle with a small circle attaching to the tip.

Non-Inverting Buffer : This kind of buffer performs no inversion or decision-making possibilities. A single input digital buffer is different from an inverter. It does not invert or alter its input signal in any way. In other words, Output will be high if and only if Input is HIGH. 

Tri-State Digital Buffer : Tri-state digital buffer has two inputs: a data input and a control input. A control works like a valve which controls the data flow. When the control input is active, the output value is the input value.

Active High Tri-State Digital Buffer : An active high tri-state digital buffer is a buffer with control input high as an active state.ONLY when the control input is 1, data transmission occurs.

What is a Level Shifter (a.k.a Translator) ?

A level shifter (a.k.a voltage level translator or logic-level shifter ), in digital electronics, is a circuit used to translate signals from one logic level or voltage domain (VDD/VSS) to another. It allows compatibility between different sub-chip blocks of ICs with different voltage requirements, such as TTL and CMOS. Modern systems use level shifters to bridge domains between processors, logic, sensors, and other circuits. In VLSI most common logic levels have been 1.8V, 3.3V, and 5V. However levels above and below these voltages are also used.

Types of Level Shifters:

Uni-Directional – All input pins are dedicated to one voltage domain, all output pins are dedicated to the other. Bi-Directional with Dedicated Ports – Each voltage domain has both input and output pins, but the data direction of a pin does not change. Bi-Directional with External Direction Indicator – When an external signal is changed, inputs become outputs and vice versa. Bi-Directional with Auto-Sensing – A pair of I/O spanning voltage domains can act as either inputs or outputs depending on external stimulus without the need for a dedicated direction control pin.

Buffer Vs Level Shifter : Comparison

The job of a buffer is to replicate a digital signal and also increase its drive strength to being degraded by other circuitry. As an example , a buffer take the signal from the microcontroller and reproduce it. Unlike the microcontroller, the buffer has a higher tolerance for being loaded down. At he same time the buffer will provide more steady output the with correct voltage for even with fast transition times. A level shifter is similar to a buffer in that it replicates signals and is drive strength is tolerant to being loaded down. However, it contains an additional feature to convert logic levels to to correct voltage value among different Voltage Domains.

Buffer Vs Level Shifter : Example

A micro-controller will use 0v and 3.3v for logic 0 & 1 levels, whereas something you want to connect which will use 0v and 5v instead. What happens when you connect the two? The micro-controller will try to communicate with the external circuit. It will send a 0 at 0v, and the external circuit will recognize the 0v as logic 0. Everything is fine so far. However, when the micro-controller sends a logic 1 at 3.3v, the external circuit may not recognize that as logic 1 since it expects logic 1 to be 5v. A level shifter comes into the picture in this situation. Now we replace the buffer with a level shifter. When the micro-controller outputs logic 0 at 0v, the level shifter will output 0v. When the micro-controller outputs logic 1 at 3.3v, the level shifter will convert 3.3v signal to  5v signal instead. The external circuit sees 0v and 5v and everything works out.

SN74LV1T34 : Logic Level Shifter

Single-Supply Voltage Translator at 5V, 3.3V, 2.5V, 1.8V VCC

Operating Range : 1.65V to 5.5V

Up Translation :

1.2V to 1.8V at 1.8V VCC

1.5V to 2.5V at 2.5V VCC

1.8V to 3.3V at 3.3V VCC

3.3V to 5.0V at 5.0V VCC

Down Translation

3.3V to 1.8V at 1.8V VCC

3.3V to 2.5V at 2.5V VCC

5V to 3.3V at 3.3V VCC

Output Drive

8mA Output Drive at 5.0V

7mA Output Drive at 3.3V

3mA Output Drive at 1.8V

Buffer Vs Level Shifter : Summary

In a nutshell a buffer tries to recreate the input signal as exactly as possible whereas a level shifter looks to alter the signal acting like a language interpreter. A buffer is just an amplifier. It takes a signal and puts out a low- impedance version of the signal. There may or may not be any actual voltage amplification. A a level shifter will translate between different standards of logic 1 & 0 of separate voltage domains.

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VHDL/System Verilog in UPF. Episode : 4

 

In this article, we cover several important aspects related to UPF and HDL simulation. We start by discussing the integration of UPF with HDL simulation, highlighting the synergy between these two critical components in power management. Next, we explore the different categories and syntax of UPF functions, providing a detailed explanation of how they operate and their significance. The article also addresses UPF supply query functions, shedding light on their role in managing power supply information. Additionally, we delve into the concepts of supply nets and data types within HDL, explaining how they interact and contribute to efficient power management. We introduce the Switching Activity Interchange Format (S.A.I.F), which is essential for analyzing power consumption. Lastly, we discuss the System-Verilog and VHDL packages for UPF, illustrating how these packages facilitate the integration of UPF into various design environments and enhance simulation capabilities.

UPF & HDL Simulation:

The voltage value and full/partial state of a supply net are valid only when its on/off state is asserted. Every time the state or voltage value of the power or ground nets changes, the power of the corresponding design elements is evaluated.

If both power and ground supply nets are on, the design element instances connected to the given supply pair are turned on. If power or ground supply net is off, the power to the design element instances is turned off. In turned off state every sequential element and every signal driven from within the powered-down element is called corrupted. Events that were scheduled before the power was turned off and whose target is inside a powered down instance shall have no effect.

UPF Functions:

UPF Functions Syntax :

UPF Supply Query Functions :

This is the verification side of UPF. Here we will see the functions that can do query to the designs.

get_supply_value : it will get the  supply value

get_supply_voltage : it will get the supply voltage

get_supply_on_stage :  it will  check the on stage

get_supply_state :  it will get the supply state

These are the UPF query functions that are required in verification.

Supply Net Data Types in HDL:

SystemVerilog:

typedef struct packed {

int voltage;// voltage in μV

bit [31:0] state;// net state 

} supply_net_type;

VHDL:

type supply_net_type is record

voltage : numeric_bit.signed(31 downto 0);// voltage in μV

state : bit_vector(31 downto 0); // net state

end record;

subtype net_state is bit_vector(1 downto 0);// the defined state bits

Supply Net in UPF:

The create_supply_net command provides an option that specifies the type of resolution to be used by the supply net.

The following resolution methods shall be provided:

Unresolved : The supply net may only be connected to a single output (this is the default).

One Hot : Multiple outputs may be connected to the supply net. At most,one of the outputs may be ON at any particular time.

Parallel : Multiple outputs may be connected to the supply net.

Switching Activity Interchange Format S.A.I.F:

SAIF stands for Switching Activity Interchange  Format. It is designed to assist in the extraction and storing of the switching activity information generated by EDA tools. A SAIF file containing switching activity information can be generated using an HDL simulator. This switching activity can be back-annotated into the power analysis/optimization tool.

SystemVerilog Package for UPF :

VHDL package for UPF:

UPF Supply Net :

VHDL Package:

VHDL Package:

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Special Standard Cells in UPF. Episode : 3

In this article , we delve into several key topics related to UPF and its interaction with standard cells. We begin by discussing the relationship between UPF and corresponding standard cells, outlining how they work together in power management. Next, we compare UPF with standard cells, providing insights into their respective roles and functionalities. The video then details the specific UPF commands associated with various types of cells, including header/footer switch cells, isolation cells, retention cells, and level shifter cells, explaining how each command facilitates effective power management. Additionally, we cover the placement of these standard cells within power domains, illustrating the strategic considerations for optimizing power distribution. Through this comprehensive discussion, readers gain a thorough understanding of how UPF and standard cells integrate to enhance power efficiency in chip design.

UPF & Standard Cells:

We will talk about four types of standard cells : Switch Cell, Isolation Cell, Retention Cell and Level Shifter Cell and their UPF commands..These are special types of standard cells. 

UPF vs Standard Cells Mapping:

create_power_switch : Header/Footer Switch Cells

set_isolation : Isolation Cells

set_retention : Retention Cells/Retention Flops

set_level_shifter : Level Shifter Cells

Power Switch Cells:

To turn OFF power supply to a power domain for a particular time of operation, we need a power switch to cut the power supply(VDD/VSS) to the domain. The create_power_switch command defines an instance of a power switch in the power domain. The switch is created within the scope of the power domain. The switch is either turned on or off as per the requirement.

Isolation Cells:

When Power Gating method is applied to a design, in a particular mode of operation, we might end up with few ON domains and few OFF domains. If the outputs of the Shutdown domain are connected to the Active Part of the design, then it might lead to Invalid Signal Transmission and crowbar current as a result. To avoid this, an Isolation Cell is placed on the output nets of Switched OFF domains interacting with an Active Portion of the Design.

Isolation UPF Command:

- The set_isolation command specifies the design elements in the domain to isolate using the specified strategy.

- isolation_supply_nets can specify a single power net, a single ground net, or both.

- If only an isolation power net is specified, then automatically the primary ground serves as the isolation ground. 

- If only an isolation ground net is specified, then the primary power net serves as the isolation power. 

-At least one of -isolation_power_net or                                   -isolation_ground_net shall be specified, unless                     -no_isolation is specified.

Retention Cells/Flops:

A retention cell is used to retain the data required in shut down power domain. A retention cell consists of a flipflop and a save latch and has two control signals, SAVE and RESTORE. SAVE signal indicates when the data should be saved in the latch, which is just before Switching OFF the power. RESTORE signal tells when the data stored in latch should be restored which is when the domain gets back to active state.

Retention UPF Commands:

- The set_retention command specifies which registers in the power domain need to be retention registers.

- Only the registers implied in the elements list shall be provided retention capabilities.

- At least one of -retention_power_net or - retention_ground_net shall be specified.

- If only -retention_power_net is specified, the primary ground net shall be used as the

retention ground supply.

If only -retention_ground_net is specified, the primary power net shall be used as the retention power supply.

If both are specified, then these options specify the supply nets to use as the retention power and ground nets.

Level Shifter Cells:

When two blocks powered with different voltage levels interact with each other, invalid signal transmissions and crowbar current generation may take place. To avoid this, level shifter cells are placed between the blocks with distinct voltage values. Level shifter cell can convert a high voltage level to low voltage level between the domains.  Level shifters are the placed on signals that have sources and sinks operating at different voltages.

Level Shifter UPF Command:

- The set_level_shifter command can be used to set a strategy for level shifting during implementation.

- Level shifter rule can be low_to_high/high_to_low or both .

- If low_to_high is specified, signals going from a lower voltage to a higher voltage get a level shifter when the voltage difference exceeds that specified by threshold .

-If high_to_low is specified, signals going from a higher voltage to a lower voltage get a level shifter when the voltage difference exceeds that specified by threshold .

If both is specified, it is equivalent to having specified both rules in the strategy.

Types of Level Shifter Cells :

Level Shifter POSITION defines where the level shifter cells are placed in the logic hierarchy. All necessary supplies need to be available in the specified location.

Self : the level shifter cell is placed inside the model/cell being shifted.

Parent : the level shifter cell is placed in the parent of the cell /model being shifted.

Sibling : a new sibling is created into which the level shifter cells are placed.

Fanout : level shifter occur at all fanout locations (sinks) of the port being shifted.

Automatic : the implementation tool is free to choose the appropriate locations.

Standard Cell Placement:

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Power Domains in UPF. Episode : 2

In this article, we explore several crucial aspects related to power domain concepts in UPF. We begin by explaining the fundamental power domain concept, providing a clear understanding of its importance in power management. The discussion then moves to the implementation of a power domain with a single hierarchical instance, elaborating on how it functions within a design. We also cover the creation of power domain instances with child elements, highlighting the complexities and benefits of such configurations. Additionally, we delve into the process of creating further hierarchy within power domains, illustrating how designers can manage and optimize power distribution effectively. This article includes a detailed explanation of the UPF power domain creation command, accompanied by a practical example to demonstrate its application. Lastly, we address the commands for creating UPF power ports and power nets, emphasizing their roles in establishing robust power connections within the design framework.

Power Domain (PD) Concept : 

Blocks which can be operated with the same power supply are identified & tied together. This forms a Power Domain. A particular power domain can be completely kept OFF or ON irrespective of the neighboring block. A power domain contains a collection of design elements that share a primary power and ground supply net. The logic hierarchy level where a power domain is created is called the scope of the power domain. Any design elements that belong to a power domain are said to be in the extent of that power domain.

PD with Single-Hierarchy-Instance:

In this case the only element in the power domain is A, which could be a Hard Macro or a Soft IP (e.g., an instance of a Verilog module).

Instance with Child Elements :

Here the scope of the power domain is the same as the extent, and the power domain is contiguous. 

- Supply port on A is created using  create_supply_port command .

- Then supply port is connected to supply net using connect_supply_net command.

- create_supply_net command applied explicitly in scope A and implicitly in U1 and U2 .

- Supply ports implicitly created on U1 and U2 to connect all the supply nets together.

PD-A contains U1/UA and U2:

Here the topology of the logic design is even more complex.  Here the power domain consists of U1/UA and U2. The two instances in the same power domain which are neither contiguous nor adjacent in the logic design, resulting in a non-contiguous power domain.

In this case, when the create_supply_net command is executed to create a supply net in the power domain, the supply net is explicitly created in A using the name specified in the create_supply_net command.

Supply ports and supply nets are also implicitly created in U1, U1/UA, and U2. The supply net in U1 connects only to the port on U1 and U1/UA.

Power Domain Creation Command:

A power domain is created using UPF command :

create_power_domain <domain_name> [-elements list] [-include_scope] [-scope instance_name]

<domain_name> The new power domain; this shall be a simple (non-hierarchical) name.

[-elements list] Use this set of design elements in the power domain.

[-include_scope] Include the scope of the domain in the extent of the power domain.

[-scope instance_name] Create the power domain within this logic hierarchy scope.

Power Domain : Example

Power Domain : Example

Power Ports & Power Nets:

- Power comes from main power sources through I/O pad-ring via Power Port.   

- The Supply Nets are used to connect Power Ports to Power Pins of each of the cells.

- create_supply_port <port_name> [ -domain domain_name ] [ -direction < in | out >]

- create_supply_net <net_name> -domain <domain_name> [-reuse] [-resolve <unresolved | one_hot | parallel>]

-reuse Extend net_name as a supply net within domain_name. No new nets are created.

-resolve <unresolved | one_hot | parallel> A resolution mechanism which determines the state and voltage of the supply net from the state and voltage values supplied by each of the individual switches. The default is unresolved.

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What is Unified Power Format ? Episode : 1

In this article, we delve into several critical aspects of UPF in the context of modern CHIP design. We start by exploring the role of UPF in today's CHIP design scenario, providing insights into its importance and application. The discussion then moves to the integration of UPF within SOC design, detailing how it is strategically placed and utilized. We also offer an in-depth explanation of what UPF is, clarifying its fundamental concepts and functionalities. Furthermore, we examine the three major types of UPF annotations, shedding light on their specific purposes and usages. Key standard UPF terminologies are explained to ensure a clear understanding of the language and practices involved. Additionally, we highlight the integration of UPF across various design stages, illustrating its significance throughout the design process. Finally, we identify and describe the four major types of UPF commands, explaining their roles and applications within the design framework.

The Scenario of Today’s CHIP :

Above diagram represents a state-of art chip. Power Management Block, Digital Block, Macro, Analog Block etc are part of it. Digital and Analog block runs on different Vdd. The Power Grid in ASIC provides power to turn on/off any VLSI chip. Power Delivery Network Carries Power towards the leaf cell such as : Standard Cells, IPs-Block or Macro-Blocks. The Power Management Unit (PMU) resides in between leaf cells and the Power Grid to control the flow of power. PMU Decides and Manages the power consumption through segregation known as Power Domains. Blocks which can be operated with the same power supply are identified & tied together. This forms a Power Domain. A particular power domain can be completely kept OFF or ON irrespective of the neighboring block. A power domain contains a collection of design elements that share a primary power and ground supply net. The logic hierarchy level where a power domain is created is called the scope of the power domain. Any design elements that belong to a power domain are said to be in the extent of that power domain. Isolation cells, Level shifter , Power switches are part of the whole system and they are very much instrumental to maintain the power domain. RTL coding is unable to express the power description of the system. UPF is used to describe power requirement of the chip.

UPF & Today’s Design :

The above diagram shows that entire design is described in two ways where functional description is done by Verilog, VHDL, Verilog AMS, VHDL AMS depending on the functional block of the system. Power intent or power description of the circuit is expressed by either UPF or CPF. Here we will talk about UPF only.

What is UPF :

UPF is an abbreviation of Unified Power Format owned by the Accellera. Any HDL do not have a way to define the power distribution/intent of a Design. UPF acts as a missing link here in filling the gap. UPF extends the logic design by adding power-aware functionality. It Annotates power distribution and power control intent. It can be defined from abstract level. It defines no routing or layout information. A UPF specification can be included with the other deliverable of an IP block. UPF contributes to Power Aware Verification.

Types of UPF Annotation:

There are three types of annotation Power Supply, Power Control and Protection. Supply Net, Supply Set, Power State are three annotation that comes under Power Supply. Power Switch is a UPF annotation that comes under Power Control. Protection can come from Level Shifter and Isolation.

Benefit of using UPF:

To allow interoperability across different EDA vendors. UPF supports Tcl syntax and semantics. UPF is constantly being evolved. At synthesis stage, special management cells are inserted in the design as per in UPF intent. At Physical Design/Implementation stage, few cells like clamp cells are added into the design as per UPF intent. 

Standard UPF Terminologies:

Design Element: Is an instance of a Verilog module , VHDL entity or a library cell. Design element is often abbreviated to element.  

Design Object (a.k.a object): A design object is any object inside the logic hierarchy. 

Design objects include : wires, registers, switches, ports, supply nets, design elements etc.

Extent: The set of design elements that comprise a power domain. 

Standard UPF Terminologies:

Power Domain: A collection of design elements that share a primary supply. A power domain may also have additional supplies, including retention and isolation supplies.

Power State Table: A table that captures the legal combinations of power states for a set of supply nets.

Scope: A particular design element in the logic hierarchy .

Regulator: A design element that takes a set of input supply nets and acts as the source for a set of output supply nets.

Current Instance: The instance specified by the set_scope command.

Design Stages & UPF: 

The above infographics shows the stages where UPF is used in SoC design flow. In SoC design at the stage of RTL design HDL and UPF commands are used. At sythesis level Gate Level Netlist and UPF is used. AT  Place and Route level we have post layout netlist or PG netlist along with UPF. Finally we have LEC (Logic Equivalence Check) , Simulation and at each stage correctness of UPF is checked throughout the design.

Type of UPF Commands:

UPF is very similar to TCL command in syntax or semantics although not very close to basic TCL commands. These are advance version of the same developed for UPF. 

There are four types pf UPF commands:

1. Power Intent Command

2. SAIF
3. Query Command

4. Test-Bench Command

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