In this article, we delve into several critical aspects of UPF in the context of modern CHIP design. We start by exploring the role of UPF in today's CHIP design scenario, providing insights into its importance and application. The discussion then moves to the integration of UPF within SOC design, detailing how it is strategically placed and utilized. We also offer an in-depth explanation of what UPF is, clarifying its fundamental concepts and functionalities. Furthermore, we examine the three major types of UPF annotations, shedding light on their specific purposes and usages. Key standard UPF terminologies are explained to ensure a clear understanding of the language and practices involved. Additionally, we highlight the integration of UPF across various design stages, illustrating its significance throughout the design process. Finally, we identify and describe the four major types of UPF commands, explaining their roles and applications within the design framework.
The Scenario of Today’s CHIP :
Above diagram represents a state-of art chip. Power Management Block, Digital Block, Macro, Analog Block etc are part of it. Digital and Analog block runs on different Vdd. The Power Grid in ASIC provides power to turn on/off any VLSI chip. Power Delivery Network Carries Power towards the leaf cell such as : Standard Cells, IPs-Block or Macro-Blocks. The Power Management Unit (PMU) resides in between leaf cells and the Power Grid to control the flow of power. PMU Decides and Manages the power consumption through segregation known as Power Domains. Blocks which can be operated with the same power supply are identified & tied together. This forms a Power Domain. A particular power domain can be completely kept OFF or ON irrespective of the neighboring block. A power domain contains a collection of design elements that share a primary power and ground supply net. The logic hierarchy level where a power domain is created is called the scope of the power domain. Any design elements that belong to a power domain are said to be in the extent of that power domain. Isolation cells, Level shifter , Power switches are part of the whole system and they are very much instrumental to maintain the power domain. RTL coding is unable to express the power description of the system. UPF is used to describe power requirement of the chip.
UPF & Today’s Design :
The above diagram shows that entire design is described in two ways where functional description is done by Verilog, VHDL, Verilog AMS, VHDL AMS depending on the functional block of the system. Power intent or power description of the circuit is expressed by either UPF or CPF. Here we will talk about UPF only.
What is UPF :
UPF is an abbreviation of Unified Power Format owned by the Accellera. Any HDL do not have a way to define the power distribution/intent of a Design. UPF acts as a missing link here in filling the gap. UPF extends the logic design by adding power-aware functionality. It Annotates power distribution and power control intent. It can be defined from abstract level. It defines no routing or layout information. A UPF specification can be included with the other deliverable of an IP block. UPF contributes to Power Aware Verification.
Types of UPF Annotation:
There are three types of annotation Power Supply, Power Control and Protection. Supply Net, Supply Set, Power State are three annotation that comes under Power Supply. Power Switch is a UPF annotation that comes under Power Control. Protection can come from Level Shifter and Isolation.
Benefit of using UPF:
To allow interoperability across different EDA vendors. UPF supports Tcl syntax and semantics. UPF is constantly being evolved. At synthesis stage, special management cells are inserted in the design as per in UPF intent. At Physical Design/Implementation stage, few cells like clamp cells are added into the design as per UPF intent.
Standard UPF Terminologies:
Design Element: Is an instance of a Verilog module , VHDL entity or a library cell. Design element is often abbreviated to element.
Design Object (a.k.a object): A design object is any object inside the logic hierarchy.
Design objects include : wires, registers, switches, ports, supply nets, design elements etc.
Extent: The set of design elements that comprise a power domain.
Standard UPF Terminologies:
Power Domain: A collection of design elements that share a primary supply. A power domain may also have additional supplies, including retention and isolation supplies.
Power State Table: A table that captures the legal combinations of power states for a set of supply nets.
Scope: A particular design element in the logic hierarchy .
Regulator: A design element that takes a set of input supply nets and acts as the source for a set of output supply nets.
Current Instance: The instance specified by the set_scope command.
Design Stages & UPF:
The above infographics shows the stages where UPF is used in SoC design flow. In SoC design at the stage of RTL design HDL and UPF commands are used. At sythesis level Gate Level Netlist and UPF is used. AT Place and Route level we have post layout netlist or PG netlist along with UPF. Finally we have LEC (Logic Equivalence Check) , Simulation and at each stage correctness of UPF is checked throughout the design.
Type of UPF Commands:
UPF is very similar to TCL command in syntax or semantics although not very close to basic TCL commands. These are advance version of the same developed for UPF.
There are four types pf UPF commands:
1. Power Intent Command
2. SAIF
3. Query Command
4. Test-Bench Command
Watch the video lecture here:
