Basic Level Shifters Cell in VLSI

In this article we will discuss about basic level shifters, their importance and working principle. Once completed you will be able to answer the below questions:

1. What is a level shifter?

2. How does a level shifter work?

3. What are different source and sink position of a level shifter?

4. What are different variants of level shifter?

                               Fig 1 : Modern ASIC/SOC Design

In modern ASIC-SOC design, different design blocks like digital, analog, macros are fabricated on a single chip and need different supply voltages for optimum performance, efficiency and speed. In multi voltage domain (i.e multi power domain) system, the logic gates on noncritical paths are operated with low VDD(a.k.a VDDL) and gates on critical path are operated with high VDD (a.k.a VDDH). Chip with different supply voltage domains use level shifters to convert and propagate logic signals among different power domains. When a logic ‘1’ signal of VDDL block drives the VDDH logic gates block, the PMOS of VDDH operating logic gate blocks may not become perfectly ON rather may lie between partially ON and weakly ON states. The level shifters are inserted at proper domain crossings to change the voltage levels accordingly to mitigate the above situation.  Also level shifters are inserted between core circuits and I/O circuits in multi-power domain chips.

Conventional Level Shifter Operation:

                            Fig 2 : Conventional Level Shifter 

The circuit diagram is a conventional level shifter thatconverts the logic level ’1’ from VDDL to VDDH.

When '1' (VDDL) is applied to the input :

1.  P5 goes OFF and N5 turns ON resulting output '0'.

2.  This '0' at node T5 is applied to N1 and turns it OFF.

3.  It is also goes to Inverter T4 which makes P4 ON and N4 OFF.

4.  The output of T4 is now '1' and is applied to N2 thus turning it ON.

5.  N2 now pulls down T2 to '0'.

6.  This turns ON P1 which, in turn, pulls up T1 to '1'.

7.  T1 is connected to the gate of P2 which now gets turned OFF.

8.  T2 remains at a value '0' which turns ON P3.

9.  P3 pulls up the value of OUT to logic ’1’ (VDDH).

Level Shifter Standard Cells :

                    Fig 3 : Placement of Level Shifters

When two blocks powered with different voltage levels interact with each other, invalid signal transmissions and crowbar current generation may take place. To avoid this, level shifter cells are placed between the blocks with distinct voltage values. Level shifter cell can convert a high voltage level to low voltage level between the domains. Level shifters are the placed on signals that have sources and sinks operating at different voltages.

Positioning of Level Shifter Cells:

                                Fig. 4: Positioning of Level Shifter

Level Shifter POSITION defines where the level shifter cells are placed in the logic hierarchy. All necessary supplies need to be available in the specified location.

i. Self :  The level shifter cell is placed inside the model/cell being shifted.

ii. Parent : The level shifter cell is placed in the parent of the cell /model being shifted.

iii. Sibling :  A new sibling is created into which the level shifter cells are placed.

iv. Fanout :  Level shifter occur at all fanout locations (sinks) of the port being shifted.

v.  Automatic :  the implementation tool is free to choose the appropriate locations.

Level Shifter Variants: 

i. Uni-Directional : All input pins are dedicated to one voltage domain, all output pins are dedicated to the other. 

ii. Bi-Directional with Dedicated Ports :  Each voltage domain has both input and output pins, but the data direction of a pin does not change.

iii. Bi-Directional with External Direction Indicator : When an external signal is changed, inputs become outputs and vice versa.

iv. Bi-Directional with Auto-Sensing : A pair of I/O spanning voltage domains can act as either inputs or outputs depending on external stimulus without the need for a dedicated direction control pin.

Well that was all about basic level shifters and lets summarize what we have discussed: 

A level shifter (a.k.a voltage level translator or logic-level shifter ), in digital electronics, is a circuit used to translate signals from one logic level or voltage domain (VDD/VSS) toanother. It allows compatibility between different sub-chip blocks of ICs with different voltage requirements, such as TTL and CMOS. Modern systems use level shifters to bridge domains between processors, logic, sensors, and other circuits. In VLSI most common logic levels have been 1.8V, 3.3V, and 5V. However levels above and below these voltages are also used. A level shifter increases the total area of the circuit, which in turn, increases the power dissipation. If voltage levels are far apart, the level shifter design becomes complex and error prone.

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Advanced Level Shifter Cell in VLSI

We have already discussed about basic level shifters in another article. Here in this article we will discuss about a little bit more complex  and state-of-art level shifters. On completion of this article you will be able to answer below questions?

1. What are different state-of-art level shifters?

2. How does a cross coupled level shifters work?

3. What is a bootstrap level shifter and how does it work?

4. Definition and working principle of DCVS Basic Level Shifter.

5. Definition and working principle of DCVS Advanced Level Shifter.

Level Shifter Philosophy:

                            Fig.1 : Level Shifter

Among multiple voltage domains, threshold voltages are also different. In order to interface between the super-threshold, near-threshold, and sub-threshold cells, appropriate level shifters  must be placed.

Level Shifter : 

The level shifter is required because the logic high output of the sub-threshold gate does not meet the minimum logic high input of the super-threshold gate.

The three combinations that are required for the hybrid methodology include interfacing:

(i)  sub-threshold to super-threshold.

(ii) sub-threshold to near-threshold.

(iii) near-threshold to super-threshold.

Clock Domain Crossings :

                               Fig. 2 : Clock Domain 

Each clock domain/voltage island can be considered as individual layer/block. Number of clock/voltage domain crossings need to be minimized. Among multiple clock domains, all the scan cells of the same clock domain are tied together. All flops in the same clock domain are also grouped together. The number of inter-clock domain lockup latches are kept fixed.

Voltage Domain Crossings :

                                   Fig. 3 : ASIC/SOC Design  

In multiple voltage islands/blocks, logic level shifter is needed to calibrate the voltage change between different voltage of logic levels. Scan-chain design in DFT for multiple voltage islands also raises the power-sequencing issue.

One solution is that power-sequencing circuitry is held to the power-on state during test operation. Another solution is that each power-sequenced island is tested independently.

The combination of multiple clock domains/multiple voltage islands needs special consideration and attention.

Cross Coupled Level Shifter :

                              Fig. 4 : Cross-coupled Level Shifter  

Conventional level Shifters are designed using cross-coupled P-MOSFETs. The incoming low voltage signal is inverted using an inverter connected to a low voltage domain (VDDL). Cross-Coupled PMOSFETs Transistors P1 and P2 are used to pull output to the high voltage (VDDH).

Boot Strap Level Shifter :

                         Fig. 5 : Boots Strap Level Shifter  

In Bootstrapping technique transient power is reduced during level shifting. Two boot capacitors Cboot-1 and Cboot- 2 replace NMOS transistors to maintain the voltage difference at the gate terminals of P2 and N2. The pull-down NMOS N2 at the output stage is driven between 0 and VDDL whereas the pull-up PMOS is driven between (VDDH − VDDL) and VDDH. Bootstrapping technique achieves lower power at the expense of significant increase in physical area due to the relatively large boot capacitors.

DCVS Basic Level Shifter:

                              Fig. 6 : DCVS  Basic Level Shifter  

One of the famous LS Design is approach is based on a Differential Cascade Voltage Switch (DCVS) level shifter. The input NMOS transistors are controlled by a low voltage input signals. This low voltage is shifted to a high voltage at the output of the level shifter.

The DCVS level shifter operates as follows. In beginning, IN = 1 and IN = 0 , OUT = 1 and OUT = 0 . Then transition happens as IN = 0 and IN = 1 , the NR goes off OFF and NL goes ON. PMOS PL remains at 0 V, maintaining PL on to resist the NL transistor by simultaneously charging node out. NR and NL is connected to the low input signal (realted to VDDL) & operate in cut-off region. Gates of PR and PL is connected to the high voltage supply. NL and NR struggle to sink more current than the PMOS pull-up transistors source. If NL sinks greater current than the PMOS pull- up transistor sources, node OUT discharges.The PR transistor toggles from the OFF state to the ON state, and charges node OUT. This cuts off the pull-up transistor PL, completing the transition.

DCVS Advanced Level Shifter: 

                              Fig. 7 : DCVS  advanced level shifter  

Here additional logic (NRT, NLT, PRT, and PLT) is added over the basic structure for improved performance. NMOS NLT and NRT are biased at a nominal voltage (VDDH). Therefore NL and NR size can be smaller than a standard level shifter. However NL and NR should be sufficiently large to force the transition within the differential structure.

When the differential input is sufficiently shifted, the significantly stronger NLT and NRT transistors complete the transition. PMOS PLT and PRT are controlled with corresponding input voltage to limit the current flowing through the full voltage pull-up transistors, PL or PR. For high input IN/IN, PLT/PRT is fully ON , providing the desired charging current. PRT/PLT limits the current, allowing the NMOS pull-down network NR/NL and NRT/NLT to discharge the OUT/OUT node.

Now lets summarize what we have discussed above ;

A level shifter ( a.k.a voltage level translator or logic-level shifter ), in digital electronics, is a circuit used to translate signals from one logic level or voltage domain (VDD/VSS) to another. It allows compatibility between different sub-chip blocks of ICs with different voltage requirements, such as TTL and CMOS. In VLSI most common logic levels have been 1.8V, 3.3V, and 5V. However levels above and below these voltages are also used. Advanced Level-Shifters such as Cross Coupled LS , Boot-Strap LS , DCVS LSetc are used as modern day level shifters.

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Retention Cell in VLSI

In this atricle we will discuss about Retention Cells in VLSI. Once completed you will be able to answer below questions:

1.What is a Retention Cell?

2. What is the importance of Retention Cell in the standard cell package?

3. How to use Retention Cell during Front end and back end design stages?

4. How many types of retention cells are used in VLSI?

Power Management Methods:

In a state-of-art chip power management inside the IC is done in several different ways. Lets take a brief look on such methods. First in the list is using multiple threshold voltages or Multi Vt. Next comes using multiple VDDs for multiple domain in the same chip. We use power gating method for managing the power between two different blocks in the same chip. We use clock gating for clock cells. Dynamic Voltage scaling and Dynamic Frequency Scaling are two other methods used for power management. Different standard cells like Retention Flop/Cell , Isolation Cell , Power Switch Cell,  Level Shifter Cell are used for power management in a chip. 

Introduction to Retention Concept:

                                 Fig. 1 : ASIC/SOC Design

When a Device/Circuit is inactive for a long period of time, a “Snooze” button helps to save the battery. Memories or registers are not capable of keeping their information while powered off. When a particular power domain inside chip is switched off, it is bound to loose its memory.  To save such scenarios special retention cells have been adopted in most of the commercial standard cell libraries (eg. TMSC, UMC, GF), to support the State retention power-gating (SRPG). Retention cells store the last state before power off of a flop inside the power domain. Thus it allows the system to continue its operation from the last known state and faster wake up of a block. The only Drawback is the Retention Mode consumes little more current than power off mode.

Retention-Cell/T-Latch/Retention-Flops : 

                              Fig. 2 : Retention Flops

Retention Cell has a flip flop and a state saving latch. Supply of flip-flop is switchable and latch is always on. The latch associated with it will retain the prior state when its power is off. The multiplexer allows us to save and restore the logic in latch. A retention cell consists of a flipflop and a save latch and has two control signals, SAVE and RESTORE.  SAVE signal indicates when the data should be saved in the latch, which is just before Switching OFF the power. RESTORE signal tells when the data stored in latch should be restored which is when the domain gets back to active state.

Power Shut Off (PSO) :

Under Power Gating comes Power Shut Off (PSO) where un-  utilized blocks are switched off completely to stop any leakage current.  PSO is triggered for any block whenever it goes to standby mode. It should be verified along with working RTL ensuring that the entire chip operates flawlessly whenever any such powered off block is turned on again. 

State Retention Power Gating (SRPG) :

To implement PSO, state retention cells are bare necessary to store existing state of the blocks before it is shutdown. During synthesis is isolation cells, retention cells, level-shifter cell and
always-on cells are inserted automatically based on CPF/UPF description.

Retention Cell in Front End Simulation & Verification :

When the verification environment launches test cases during simulation different power states are entered.  The modules in the supply network propagate their state through out the network. It generates the power management signals:

a) enable the Power Switches and of the Isolation cells. 

b) save the State in Retention cell (to store registers values before their shutting off).

c) restore from State Retention cells (to retrieve registers values once switched on).

These information is coded during the CPF/UPF file creation. Monitors inside each module such as power switches, isolation and retention record and log the sequence of events. After simulation the logged events are automatically evaluated and checked. Any activity found inside a deactivated domain is reported immediately.

Retention Cell in Back End (Physical Design):

While the system is created, the power design is coded in UPF/CPF. Power switches to change domain supply states are created. Power domains are described and connected to the supply network. After the floor-plan completion, all its specifications are dumped onto a Design Exchange Format (DEF) file. The inputs to the placement tool are the gate-level net-list, floor-plan DEF file, power intent file, timing module files, and reference library files. Sanity checks are performed on the floor-plan file and gate-level net-list. The power intent file is checked and any violations between the floor-plan data, gate-level net-list, and power intent are corrected. The floor-plan information is then loaded onto the Back-end EDA tool. Next, the power intent is committed, which adds the isolation cells, retention cells, enable Level Shifter, and Power Multiplexers.

Types of Retention Cell Latch :

Balloon Latch
Master-Slave Latch

Balloon Type Retention Cell : 

In a “balloon” type retention register, the retained value is held in a shadow or additional latch, often called the balloon latch and usually powered by the -retention_supply. A “balloon” type retention register typically has additional controls to transfer data from a storage element to the balloon latch, also called the save stage. And transfer data from the balloon latch to the storage element, also called the restore stage. The ports to control the save and restore pins of the balloon-style retention register need to be available in the design to describe and implement this type of retention registers. The balloon element is not in the functional data-path of the register.

Master-Slave Type Retention Cell : 

A master or slave-alive retention register, the retained value is held in the master or slave latch and also powered by the –­retention_supply. In this case, the retention element is in the functional data-path of the register. A “master or slave-alive” type retention register typically does not have additional save or restore controls as the storage element is the same as the retention element. Additional control(s) on the register may park the register into a quiescent state and protect some of the internal circuitry during power-down state, and thus the retention state is maintained. The restore in such registers typically happens upon power-up, again owing to the storage element being the same as the retention element. Thus, this style of registers may not specify save and (or) restore signals, but may specify a retention condition that could take the register in and out of retention state.

Now lets summarize what we have discussed : 
Retention cell is an integral part of the present Standard Cell Library used in ASIC Design. It is a must for the chips where there are multiple Power Domains are existing. In the Power Aware RTL design retention cell is equipped through UPF/CPF. There are two major types of the Retention Cell : Balloon Type and Master-Slave Type.

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Isolation Cell In VLSI

In this article we will discuss about Isolation Cell and their importance in VLSI. Once completed you will able to answer the following questions:

1. What are isolation cell and why they are important?

2. How many types of isolation cells are there in commercial 

    standard library?

3. Why an isolation cell is bare necessary in a multiple power        domain chip?

4. How Isolation cell is associated with power aware RTL       

    verification?

Power Management Methods:

In a state-of-art chip power management inside the IC is done in several different ways. Lets take a brief look on such methods. First in the list is using multiple threshold voltages or Multi Vt. Next comes using multiple VDDs for multiple domain in the same chip. We use power gating method for managing the power between two different blocks in the same chip. We use clock gating for clock cells. Dynamic Voltage scaling and Dynamic Frequency Scaling are two other methods used for power management. Different standard cells like Retention Flop/Cell , Isolation Cell , Power Switch Cell,  Level Shifter Cell are used for power management in a chip. 

Problem Scenario Among Power Domains :

Fig. 1 : Power domains  

Inter-domain signals can become complicated if the connecting interface changes during different power modes. During Power Gating operation, the circuit will contain few ON domains and few OFF domains together at any point of time. In such situation, output of a OFF domain sends invalid signal to the ON Domain.

When this floating voltage is propagated to the inputs of the receiving end, a short-circuit current is produced. Crowbar Current may flow because output pins of OFF domain might be in the meta- stable/dangling state.

Isolation Cell To The Rescue : 

To deal with such problematic situation specially designed Standard Cell (a.k.a Isolation Cell) is placed between power gated block and the active block. An Isolation Cell clamps the signal at its input pin to a defined known state, either logic "0 ‟ or logic "1". Hence transmission of invalid signal is eradicated. Controllers are used to control and synchronize local power switches and isolation cells with clock gating or power gating signals.

                              Fig. 2 : Importance of Isolation Cell   

Two types of controllers are used in VLSI :

i.  Simple adaptive controller

ii. Enhanced adaptive controller

Isolation Method and Isolation Cell:

                                  Fig. 3 :  Isolation Cell  

When Power Gating method is applied to a design, in a particular mode of operation, we might end up with few ON domains and few OFF domains. If the outputs of the Shutdown domain are connected to the Active Part of the design, then it might lead to Invalid Signal Transmission and crowbar current as a result. To avoid this, an Isolation Cell is placed on the output nets of Switched OFF domains interacting with an Active  Portion of the Design.

Detection of Missing Isolators :

                                   Fig. 4 : Missing Isolators 

The isolation and level shifter strategies  are defined at RTL stage itself in UPF/CPF  file. In UPF/CPF if an isolation and/or level shifter strategy is to be defined between power nets connected to source and sink  domains. Unable to do so the resulting in malfunctioning of the design. Such  scenarios are detected by standard EDA  tools and an error is flagged.

Isolation Standard Cell Example : 

Fig. 5 : Isolators Standard Cell

Drawbacks & Improvements :

                          Fig. 6 : Isolation Cell and Level Shifters

Isolation cells need to be inserted at the interface of different power domains. This adds significant area and power overhead. The AND/OR isolation cells, require more area. To lower the area overhead, the isolation cells use an NMOS pull-down transistor. Using high VT transistors further lowers the leakage current caused by the inactive isolation cells.

So that was all about Isolation Cells. Now lets summarize what we have discussed here :

Conventional techniques are applied to perform electrical checks for voltage crossing domains and power islands. Voltage level shifter, electrical isolation cells, retention cell etc are applied in through Power Aware RTL using CPF/UPF. Isolation cells (ISO) enable electrically safe power shutdown states from affecting powered-on regions, by fencing off the propagation of non-deterministic logic states.Two types of Standard Cells isolators are used : OR/AND Types.

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What are IP Views in VLSI ?

While working in VLSI, we need to handle a lot of files with various file extension. All these files are actually different views required in the VLSI design. In this article we will discuss about those views  and their utilities in brief. 

IP Views :

When we receive a design kits there weill be different files with various extensions. We need to know which file is required for  which tool. Here we will talk about front end Rtl views, front end timing views and also backend views like  Layout Views, Physical verification views Phy-Ver Views, Parasitic extraction Views and finally Compiled Macro Views.

Each Different EDA Design Tool requires specific format of input files and they generate specific output file with particular file format. All proprietary tools have their own file format and file meant for one tool is not compatible to any other tool. The same unit cell , while passing through various stages of design requires specific format as per the stage. EDA Tools have their propitiatory format for each unit cell or block of the design. This restricts a end-user to stick to same-vendor and this is a business move rather than technology need. Most big houses use multiple commercial tools meant for same work (obviously from top competing vendors) for a step. So in such case multiple files are required with different extensions for same step.

Front-End Views : 

1. RTL  :

Verilog and VHDL views are two most common and popular views in front end. For assertion and and other capabilities system verilog view is most important. For every unit cell all types of definition with proper extension is available in the library. DB,SDB, SLDB are also some front end views. Here mentioned *.db, *.sdb and *.sldb all three are is Synopsys database format.

Other front end views include UPF (Unified Power Format) , CPF (Common Power Format), OA (Open Access) etc. We have a playlist on UPF. You can watch here.

2. Timing views : 

Timing views are contained in the .lib files. There will be corner wise variation like fast-fast, slow-slow, typical-typical etc. We all know in PVT (power, voltage and temperature) there are three corners like slow,fast and typical.  In the .lib files there are variations of how the look up table are taken care of .Different timing models are there and as well the extension of the lib files are different like *.ocv, *.nldm, *.ccs, *.ecsm , *.nldm , *.ccs, *.ecsm are basically timing models.

nldm stands for non-linear delay model

ccs stands for concurrent current source

ecsm stands for equivalent current source model

ocv stands for on chip variation

aocv stands for advanced on chip variation.

3. Transistor Level  Views :

*.cdl and *.spice are two different extension of files with transistor level data. Generic transistor level netlist is SPICE or  CDL. Both are  representation of a circuit with transistor level data.  Specific tool compatible view could be HSPICE or ELDO or SPECTRE.

Back End View : 

Now lets talk about back end view. Back end covers all the steps between syntheses ans tape-out.  All the layout, timing, physical verification are done at back end so the number of back end views are higher when we compare them with front end views.

1. Layout Views :

The layout views are created with layout editors. The first file we can find in layout view is mapping files. These mapping file generally contains various layers and numbers. NDM,DB, GDSII are other layout views. Synopsys tools use *.db files. Whereas Cadence tools uses *.lef and *.def files. OASIS view is much more generic view. There could be CIF files and abstract view. The design kit can contain some of them, many of them or all of them. How many files would be there in the kit depends on which tool or tools are used. 

2. Physical Verification Views:

Some most popular physical verification tools are Voltus, Redhawk, Asura,  Calibre, Herculis, ICV etc. Depending on the design need and customer demand a design house could use multiple of them. So the design kit contain views and files compatible to the tools.  

3. Parasitic Extraction (PEX)  Views:

Some parasitic extraction views are *. spef, *.dspf and *.sbpf.

SPEF stands for Standard Parasitic Extraxtion File

DSPF contains transistor level parasitic extraction data and generally compatible to SPICE tools

SBPF is a binary format and used by Synopsys tools. 

4. Macro  Views :

More generically these are called compiled macro views. The word compiled is used as there are compilers that compile these views.  NVM, SRAM, DRAM etc. Are some semiconductor memories that might have compiled macro views. 

Now lets summarize what we have discussed so far. Views are basically file formats. They are used to felicitate as many as tools possible.  Variation of views may be different from one technology node to another technology node. No of views may vary from one standard cell vendor to another. Same view of associated with a particular tool may become incompatible over time due to fabrication-technology related changes inside the tool. So always use the latest library with up-to-date version of the views.

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Electro Static Discharge in VLSI

In this article we will discuss about ESD EVENT in an IC. We will try to understand what happens in case of ESD event inside the the chip at device level. We will also discuss about different types of  ESD protectors.

1. Electrostatic Discharge (ESD) :

In  the most simplistic word , Electrostatic Discharge (ESD) is the release of stored static electricity. The most famous type of ESD (large scale) is lightning which voltages up to 10^7 V and currents up to 30 kilo-amperes. Electrostatic charging of two objects results from electron transfer during friction. ESD is the electrostatic event  which balances the charge potential difference between two charged objects with opposite polarity and leads to a high current for a very short time.

The incident of lightning we can see with our bare eyes whereas the  ESD event that take place in chip is not visible. On an average ESD destroys about 20 % of electronic components before they are installed into a system. After assembly, anywhere from 33 to 70 % of digital devices fail soon after customers purchase because ESD may only damage a component but it opes the door to further subsequent damages within a brief time during circuit operation.

A person can acquire charges by simply walking across a room. When such a charged person or object then approaches a  grounded conductor, for example a pin of a packaged Integrated  Circuit (IC), an Electrostatic Discharge (ESD) event  occurs, characterized by a high current ( ∼ A) within a few ns. A high current density and/or electric filed can damage conductor, semiconductor and insulator in an IC.For this reason electrostatic straps are used in industry where electronics circuits are packaged and assembeled.

A human's sensory perception cannot recognize the several thousand volt discharge of ESD.

The circuit present inside the IC, will tend to be partially damaged or might breakdown when this high voltage pulse enters. When we buy different semiconductor component for computers we get it in a dark grey package , that is basically a external protection for ESD event. In this article we will talk about internal protection for ESD.

                       

Fig 1. ESD waveform

2. ESD Damage & Protection :

ESD in an IC is usually start with the oxide breakdown which result in percussion path. The high current density damages the semiconductor devices through thin-film fusing,filamentation, and junction spiking. The high electric field, on the other hand,can cause failure through dielectric breakdown or charge injection. Dielectric is used in an IC for MOS structure, isolation etc. ESD can damage any dielectric in IC. Hence necessary components are used to protect ESD so that the destruction of a product or system when touched can be eliminated. Due to this factor, there is a strict packaging, handling and design requirements on suppliers by Govt and many other companies. The below picture shows typical I/O schematics protected by ESD cells. Vdd, Vss, I/O Pads are actually connected to IC periphery. Core of the circuit is shown in the middle and Clamp is on the other side. This a typical arrangement of ESD protection scheme.                                           

                     Fig 2. ESD stack diode

                             

3. Various ESD Damages :

Lets discuss some damages take place due to ESD event. 

i.  Junction Burn Out  :

Junction Burnout is caused by the injection of an ESD transient of sufficient energy and duration to  force the junction into secondary  breakdown. Junction burnout is often characterized by high reverse bias leakage current or a total short.

ii. Oxide Punch-Through :

Oxide punch-through is the other major category of ESD damage. Oxide punch-through occurs when an oxide is subjected to an ESD pulse of a high enough magnitude to cause the oxide to breakdown. Transient domain of an ESD event, the voltage applied the gate oxide must be very large to initiate oxide breakdown.

iii. Metallization Burnout :

Metallization burnout is often a secondary effect, occurring after the initial junction or oxide failure took place. Metallization burnout occurs if the current flowing through the metal forces the temperature to rise, due to the I2R power calculation, high enough to reach the melting point of the material.

4. Characteristics of a good ESD protector :

A good ESD protector must - 

 i.    Clamp the ESD voltage to shunt the ESD stress current

 ii.   Turn-on fast enough

 iii.  Can carry large currents

 iv.   Have low turn-on-resistance and minimum series resistance

  v.   Occupy minimum area at the bond pad

 vi.   Have minimum capacitance

 vii.  Standout robust against for numerous pulses

viii.  Not interfere with IC functional testing.

5. ESD Protection In VLSI Design :

ESD Design Rules:

The protection design implementation becomes complicated for different I/O signal configurations. Also, placement of unrelated circuits near an I/O pad causes unexpected current paths through interactions and may render the protection device ineffective. The same could occur in the internal connections between the power supplies, preventing the power supply clamp from operating. All of these issues are covered in ESD design documents so that product ESD design is addressed properly from the beginning.

ESD Protection is done using several types of IO Cells such as:

i. Digital I/O Buffers : Provide High drive up-level shifting output. Provide down-level shifting and ESD protection for inputsii. Analog I/O Cells : Provide ESD protected analog inputs/outputs

6. ESD Protection Methodology :

The main goal of ESD protection circuits is to provide a low-resistive discharge path. Figure shows the typical chip-level ESD protection scheme in which an ESD power supply clamp is connected between the two power rails under different ESD stresses. The ESD clamp provides the discharge path for an ESD event that happens between the two power rails.

Clamps could be of category: 

  (i) Static clamps                  (ii) Transient clamps.

The static ESD clamps turn on once the voltage across the supply rails exceeds the triggering voltage and start conducting the current of the ESD event.

The transient ESD clamps take advantage of the rapid change in voltage during an ESD event to trigger  the clamp using a rise time detector and a delay element to keep the clamping element on during the entire  ESD event. Transient clamps are able to react fast; however, these circuits must be carefully designed to keep their  leakage to minimum.

7. ESD Protection Schemes : 

i. Diodes

Turn-on Type Device (Zener Diodes): 

A turn-on device like diode turns-on after reaching a particular trigger-voltage. 

Once the device is turned-on, it offers a low  impedance path for the ESD current to flow.

The Current-Voltage (IV) characteristic for such a device is shown in Figure. Diodes offer 

a simple and effective turn-on type ESD protection. They can be used in either the forward-biased 

or reverse-biased configuration since diodes have the I-V characteristics as shown in Figure.

They offer a low resistance path. The advantage of this method is that it can be simulated using SPICE. One limitation is the fixed diode turn-on voltage which can reduce the application of the diode for this.

8. Stack Diodes :

Figure shows an ESD protection structure consisting of stacked diodes. Under normal operating conditions, the diodes are reverse biased and hence in the off-state. During an ESD event, the diodes forward bias and divert the ESD-induced current  away from the internal circuit. The drawbacks of such a structure include the relatively large on-state resistance and added complexity in optimizing the interconnect metallization parasitic for advanced CMOS process technologies.

9. Snapback Type Devices : 

Snapback type protection schemes are capable of handling higher currents.

Grounded-gate NMOS (ggNMOS), gate-coupled NMOS (gcNMOS), SCR (Silicon controlled rectifier) are ESD protection devices which work based on snapback mechanism.

5 Different Types of SCR are used for ESD protection:

 i.    Low-Voltage Triggered SCR (LVTSCR)

 ii.   Gate-Coupled LVTSCR

 iii.  Substrate Triggered SCR (STSCR)

 iv.  Double Triggered SCR (DTSCR)

 v.   Boundary MOS Triggered SCR

10. Silicon Controlled Rectifier (SCR) : 

SCR which provide the high value of the area gain factor compare with other protection structures.

SCR is commonly used for ESD protection in advanced processes technology.

However, a SCR has high triggering voltage of approximately 20V compared to low holding voltage about 1~2V. SCR is popular for its area efficiency: with same ESD protection level SCR occupies smallest area among the three basic devices. The cross schematic view and the equivalent circuit of a SCR are shown in Figure, in which consisting a PNPN structure. After trigger, the SCR will exhibits a snapback I-V characteristics as shown. Typically, SCR has large snapback.

11. Gate Grounded NMOS (GGNMOS) : 

To solve ESD problem, GGNMOS (Gate Grounded NMOS) is commonly used in protection device. GGNMOS is easy to design and is perfectly compatible with CMOS processing.

However, it consumes relatively large silicon area because of the low current driving capability.

Due to GGNMOS has simple structure and it is compatible with CMOS technology, it is also a popular device in ESD protection. GGNMOS is modified from the normal NMOS device.

In GGNMOS, the drain of NMOS serves as the anode, and the shorted gate, source and body contact are tied together to serve as the cathode.

             

12. ESD Protection Schemes : Clamp

ESD Protection Circuit :

There are different on-chip protection methods used for ESD protection. The rail-based ESD protection circuit is one among them. Placement of the power supply clamps determines the effectiveness of the IO protection in a rail-based ESD protection arrangement.

Power Clamp :

Power clamps are present inside each power supply IO. They are used to shunt current to ground from power supply lines when an ESD event occurs or any event which can potentially damage the electronic components. The RC-triggered power clamp is a simple and efficient implementation to achieve the same.

Courtesy : Image by Philippe Donn from pexels 

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