On-Chip Inductance in VLSI PD : Interconnect Series - 3

 

With gradual down-scaling of MOS devices,  parasitic effects specially inductive parasitic effect becoming more and more significant. In this article we will discuss about on chip inductance.

How On-Chip Inductance Become Significant?

On-Chip Inductance effects have become increasingly significant because:

1) Some global signal and clock wires have large widths and thicknesses at the top level of the metal to minimize delays. This decreases the resistance of the wires, making their inductive impedance comparable to the resistive part. There is more to impedance than resistance: Z = R + jωL . When ωL is comparable to R, inductive effects must be considered.

2)As the clock frequency increases and the rise times decrease, electrical signals comprise more and more high-frequency components, making the inductance effects more significant.

3) Signal transition times become much shorter (comparable to the signal time of flight) and devices become faster.

4) With the increase of chip size, it is fairly typical that many wire are long and run in parallel, which increases the inductive Cross talk and delay.

5) With the push of performance, some low-resistivity metals,e.g. Cu wires, have been explored to replace Al in order to minimize wire RC delays. This could make the wire inductive reactance larger than the resistance.

Interconnect Model Mapping with Tech. Nodes:

Loop & Partial Inductance:

Loop Inductance: Loop inductance is defined as the induced magnetic flux in the loop by the unit current in other loop,

where, ψ ij represents the magnetic flux in loop i

due to a current I j in loop j.

Partial Inductance:

Proposed by A. Ruehli (Partial Element Equivalent

Circuit (PEEC) method). Partial inductance is the portion of loop inductance for a segment when its current returns

via the infinity. It can be directly applicable to circuit simulator

like SPICE

Problem with loop inductance:

Calculation of loop inductance require knowledge of return paths. Its really difficult to determine return path for on-chip interconnects explicitly since there in no ground plane. Almost every wires couples to many wires, and there are multiple return paths.

Properties of Partial Inductance:

Partial self and mutual inductance are based on geometry only. They may be solved by using a 2D/3D field solver. The return path or the current loop may be determined through SPICE simulations. The partial self and mutual inductance may be frequency and proximity dependent.

Transmission Line  Model :

The inductance is distributed over the wire, like R and C. A transmission line model, becomes the most accurate approximation of the actual behavior. In TL Model , a signal propagates in interconnection medium as a wave:

For most insulating materials leakage conductance g=0, and eliminating the current i yields the wave propagation equation:

where r, c, and l are the resistance, capacitance, and inductance per unit length respectively. 

For the lossless Transmission line, r= 0 and the equation becomes:

Step input propagates with speed,

Values of both l and c depend on the geometric shape of the wire, their product is a constant and is only a function of the surrounding media. The propagation delay per unit wire length (tp)of a transmission line is the inverse of the speed:

Dependence of Impedance on Frequency:

In a circuit with multiple current paths the distribution of the current flow is frequency dependent 

– at low frequency current path is determined by the resistance of the paths 

– at high frequency current path is determined by the inductance of the paths

This effect is the primary source of inductance variation with frequency in integrated circuits.

Impact of On-Chip Inductance:

 Any current passing through a conductor creates a magnetic field. This magnetic field then induces a parasitic current either on the same metal (i.e self-inductance), or on another metal crossing the magnetic field (i.e., mutual inductance).If we focus on resistance and inductance, we can express interconnect impedance as: Z= R+jwL

1. Skin Effect : A high frequency phenomenon. As frequency increases, the current tends to flow closer to the conductor  surface or skin, between the outer surface and a level called the skin depth. It is defined as the depth where the current density is just 1/e (about 37%) of the value at the surface.  Skin effects increase the resistance parasitics of a conductor at at high frequency. They also lead to a frequency-dependent value for the effective inductance and resistance seen by the current. Such effects must be included in the parasitic extraction to achieve accurate results.

Proximity Effect : When two or more conductors carrying a.c are close to each other, then distribution of current in each  conductor is affected due to the varying magnetic field of each other. The varying magnetic field produced by a.c. induces eddy currents in the adjacent conductors. When the nearby conductors carrying current in the same direction, the current is concentrated at the farthest side of the conductors. When the nearby conductors are carrying current in opposite direction to each other, the current is concentrated at the nearest parts of the conductors. This effect is called as Proximity effect.

The proximity effect also increases with increase in the frequency. Effective resistance of the conductor is increased due to the proximity effect.

Difficulties with Inductance:

It Depends on Frequency. Inductance of a Wire Requires Knowledge of Return Path(s). The Vss or Vdd closes loop for each piece of interconnection. The return path is decided by signal pattern and interconnect geometry for a large range.  Often return path is not easily identified, particularly at layout stage as it is not necessarily through the silicon substrate. Silicon substrate cannot be considered as a ground plane as the resistivity of the doped substrate layer is very high compared to metal and the substrate is too far away from the high-speed buses or clock wires. Mutual Couplings Between Wires Decrease Very Slowly. Magnetic fields die out at a far distance as compared to the electric fields.  Considering near neighbors which is enough for capacitance is not enough for inductance. Reason of concern for high frequency designs. Inductance is not scalable.   Inductance results in many high frequency poles and zeros, making Reduced Order Model Approximation difficult.

Minimizing On-Chip Inductance:

1. Dedicated Ground Wires : Increase the mutual inductance by making the signal wire and its return path to be as close as possible. Decrease the self Inductance by increasing the width of the return path, or by adding one or more ground wire in between signal wires.

2. Differential Signaling : This method has high signal-to-noise ratio due to the common mode noise rejection, however, requires double the number of signal paths as compared to single-ended transmission networks. The transmitter
at the near end of the network converts the single-ended signal into an opposite polarity differential signal, while the receiver at the far end of the transmission lines converts the differential signal into a single ended form.

3. Splitting Wires : Splitting a wide wire into several N parallel wires of about two skin depths width each may reduce the total reactance by a factor of N.

4. Continuous Power / Ground Planes : When signals travel a long distance for current return without planes nearby that causes inductive coupling. A continuous power/ground plane greatly  reduces the coupling.

5. Buffer Insertion :  With inserted buffers, inductive coupling decrease slightly faster than a linear rate. Each segment becomes more an RC line than an RLC line. Because L per segment scales down at a rate faster than the R,C.

6. Shielding : Shielding techniques are widely used to reduce capacitive and inductive coupling. Isolates an aggressor/noisy line from sensitive neighboring lines. Increases the noise tolerance of a sensitive line. The voltage of the shield lines typically does not switch. By inserting a shield line between signals lines,  changes in the effective interconnect capacitance is significantly reduced, resulting in less delay uncertainty. Inductive coupling and self inductance can also be reduced by inserting shield lines, since the shield line provides a nearby current return path.

7. Termination :The behavior of the transmission line is strongly influenced by the termination of the line. The termination determines how much of the wave is reflected upon arrival at the wire end. This is expressed by the reflection coefficient ρ that determines the relationship between the voltages and currents of the incident and reflected wave forms.

where R = termination resistance

Z0 = characteristic impedance

i) If R= Z0 , ρ=0 , the termination appears as an infinite extension of the line, and no waveform is reflected.

ii) If R = ∞ , ρ = 1. The total voltage waveform after reflection   is twice the incident one.

iii) If R = 0 , ρ = -1. The total voltage waveform after reflection equals zero.

Significance of Termination :

To reduce the coupling noise at the inputs of victim receivers diff. termination methods are used:

1) Series RC Termination,

2) Series R Shunt C Termination,

3) Series R Termination, 

4) Diode Termination

Termination is really important to prevent ringing effect when signal or data travelling long path. Ringing is generated on the transitions of digital signals when a portion of the signal is reflected back down the line due to a mismatch between the line impedance and the terminating impedance. A similar mismatch at the driving end will re-reflect a further portion towards the receiver, and so on.

The amplitude of the ringing depends on the degree of mismatch at either end of the line while the frequency depends on the electrical length of the line.

Modeling of Interconnect at High Frequencies

At high frequencies circuit dimensions become comparable to signal wavelengths and it is not always possible to identify discrete parasitic element. There are some models used to extract parasitics at high frequencies: 

1)Field Solver

2)Finite Element Method

3)Moment Method

4)Boundary Element Method (BEM)

5)Finite Difference Time Domain (FDTD) Method

6)Transmission Line Matrix (TLM) Method)

7)Partial-Element Equivalent Circuit (PEEC) Method

Watch the video lecture here : 

Courtesy : Image by www.pngegg.com

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Interconnect Delay Modeling in VLSI PD : Interconnect Series - 2

  

In this article we willl discuss about delay models in interconnects. I/P to O/P delay in IC has 2 components : gate & interconnect delay

Gate Delay : 

Signal transmission through a gate is not instantaneous. The time required for signal to travel from input of the gate to output of the gate is Gate delay or propagation delay.

The figure shows a Gate /Propagation delay of NOT gate. O/P changes after a delay of “DELTA” with change in I/P. Gate delay is not equal for high to low and low to high transition.

Wire Delay :

Interconnects or wires connecting active devices add delay while carrying signal. This is wire delay. Wire delay is also known as transport/ flight delay. Wire delay become dominating with higher operating frequency i.e., lower device dimension.

Delay Models :

RC Network and Gate Delay Modeling :

RC circuits are frequently used to model the timing  characteristics of ICs. When one logic gate drives another gate, the input ckt. of the second gate can be modeled as an RC load. The propagation delay through the first gate is calculated by assuming Vin as ideal square wave and the RC load. Gate delay is inversely proportion to the switching speed of the gate.

RC Network and Wire Delay Modeling :

A wire can is modeled as many cascaded sections of simple RC circuits. When a square wave is applied to one end of the bus, it takes time to propagate. This delay time due to the wire can be calculated based on the values of R and C in each section and the number of sections used to model the wire. The longer the wire, the more sections are needed for accurate model. 

Wire load Model (WLM) : WLM is used to estimate delay based on area and fanout. Semiconductor vendors develop wire load models. Used in pre layout design cycle.

Lumped C Model : 

Ckt. parasitics of a wire are distributed along its length and are not lumped into a single position. 

Lumped Model is considered in a circuit where :

i. single parasitic component is dominant

ii. interaction between the components is small iii. one aspect of the circuit behavior is considered

Effects of the parasitic can be described by an ordinary differential equation. If parasitic R is negligible and ckt. is operating in low to medium range, only capacitive component is considered. Distributed capacitance lumped into a single capacitor. That is Lumped C Model. Suited well for older tech node where wires were wide. High cross sectional area A ( H X W) means less R.

In this model wire is equi-potential region & wire does not introduce any delay. Impact on performance is introduced by the loading effect of the capacitor on the driving gate. This capacitive lumped model is simple and effective.  Model of choice for the analysis of most interconnect wires in older tech node.

Lumped RC Model:

Lumped RC model is used when : (i) wire length L > few mm, (ii) resistive component is considerable. With scaling wire cross section is reduced & R become considerable. Lumped C model is inadequate.

Interconnect is modeled with resistive capacitive/RC model. Multiple approaches are there depending on complexity and operating condition of the ckt and verified with accuracy of the result. In lumped RC model the total resistance of each wire segment is lumped into one single R and global capacitive is combined the into single capacitor C.This model is pessimistic and inaccurate for long interconnect wires, which are more accurately represented by a distributed RC model.

RC Networks :

Studying lumped RC network is important as, the distributed RC model is complex and no closed form solutions exist. The behavior of the distributed RC line can be, adequately modeled by a simple RC network. A common practice in the study of the transient behavior of complex transistor-wire networks is to reduce the circuit to an RC network. Analysing such a network effectively and to predict its first-order response is important for designers. Two popular Network : Tree Network & RC Chain/Ladder Network

Pi and T Models:

The distributed RC delay can be modeled by breaking up a wire into one or more segments and using a lumped model for each segment. Popular lumped models are Pi and T model (named for their shapes). R and C depend on the length of the segment. Pi and T model, are both good models. Although Pi model is slightly more convenient because of fewer circuit nodes. Most circuit simulators have built-in distributed rc-models of high accuracy.

Elmore Delay Model :

Derived originally in the 40s for circuits applications and applied in 80s for RC trees. Elmore defined delay through linear network as the first moment of the network impulse response. The Elmore delay formulas are immensely useful and simple model.  Layout peoples use in algorithms( Single time constant). More accurate compared to simple length-based schemes. Although later verification required (not super accurate! ) with higher order models that incorporate more than one time constant.

Simple RC model provides general approximation of timing behavior of digital integrated circuits Elmore delay model is used in order to improve accuracy of RC model. Here, the RC segments made up of series resistance Rn and a capacitance Cn are created. Think of current like real water, flowing in tree. From any component of tree,looking at the source, it’s UPSTREAM & look toward leaves, its DOWNSTREAM.

RC Tree Network with Elmore Delay:

Wire branching into many destination modeled as an RC tree. Its a tree of resisters. Root of the tree is at the source node S where input signal is applied. There is no loop. At the branch end output is measured. Each intermediate node is grounded with a capacitor. There exists a unique resistive path between the source nodes and any node i of the network. The total resistance along this path is called the path resistance Rii.

The path resistance between the source nodes and node 4 is expressed as , R44 = R1+R3+R4. 

The path resistance of the shared path can be expressed as resistance Rik = effective resistance between the input and node k in common with the path between the input and node I :

So using above formula Ri4 = R1+R3 ; Ri2 = R1. The Elmore delay from the source to node i of an RC tree is given by :

 

N = number of nodes in the tree, Ck = capacitor on node k , Rki = shared resistance between node k & I.

Elmore delay for network = Tdi = R1C1+R1C2+ (R1+R3)C3+ (R1+R3)C4 + (R1+R3+Ri)Ci

RC Chain with Elmore Delay Model :

A special case of the RC tree network : non- branched RC chain or ladder. In digital circuits similar structure is found. Represents an approx model of a resistive-capacitive wire.  

The delay component of : 

Node 1 = C1R1 ( R1 is the total resistance between the node 1 and the source)

Node 2 = C2(R1+ R2) ( R1+R2 is the total resistance between the node 2 & source )

Delay = Sum (Cap i * Resistance from Source to Cap i)

= R1C1 + (R1 + R2) C2 +...+ (R1 + R2 + R3+...+Ri) Ci

This gives the right answer for all values of C and R unless R or C have value equal to 0. t is the only equation that is correct in all the limits.

Distributed RC line Model :

A distributed rc line model is a more appropriate model. r and c stand for the resistance and capacitance per unit length. The voltage at node i of this network can be determined by solving the following set of partial differential equations:

by reducing asymptotically to 0 , we get , 

where V is the voltage at a particular point in the wire, and x is the distance between this point and the signal source.

These equations are difficult to use for ordinary circuit analysis. The distributed rc line can be approximated by a lumped RC ladder network,which can be easily used in computer-aided analysis.

Transmission Line Model :

The inductance is distributed over the wire, like R and C. A distributed rlc model of a wire, known as the transmission line model, becomes the most accurate approximation of the actual behavior. In Transmission Line Model , a signal propagates in interconnection medium as a wave (In distributed rc model, where the signal diffuses from the source to the destination governed by the diffusion equation) . In the wave mode, a signal propagates by alternatively transferring energy from the electric to the  magnetic fields, or equivalently from the capacitive to the inductive modes. 

Assuming that the leakage conductance g equals 0, which is true for most insulating materials, and eliminating the current i yields the wave propagation equation:

where r, c, and l are the resistance, capacitance and  inductance per unit length respectively.

Consider the point x along the transmission line of figure as shown above at time t. The following set of  equations holds:

Lossless Transmission Line :

For the lossless Transmission line, r= 0 and the previous equation simplifies to the ideal wave equation:

Step input propagates with speed ν

Values of both l and c depend on the geometric shape of the wire, their product is a constant and is only a function of the surrounding media. The propagation delay per unit wire length (tp ) of a transmission line is the inverse of the speed:

Watch the video lecture here :

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