Exploring Interconnects in VLSI PD : Interconnect Series - 1

For last few decades minimum feature size of MOSFETs has reduced from 10 μm to much less than 10 nm . The main purpose of continuous scaling of the device dimensions is to improve the performance of IC and to pack more devices in the same area. The cost per transistor has decreased by seven orders of magnitude, and the maximum number of transistors per chip has increased by at least 10 orders of magnitude. However, as the technology node is advanced, the interconnect of ICs becomes the bottleneck in the improvement of IC performance. In this article we will discuss about interconnects and their impact on VLSI design and IC performance. 

Basics Of VLSI Interconnects:

Active devices and regions in IC are electrically connected to each other to make circuit. They are also connected to the outside world through their I/P and O/P on bonding pads. Contacts, vias and interconnects used for such connections. Contact is connection to source, drain or poly. Vias are connections between interconnect levels. Interconnects are separated from each other by dielectric layers. Dielectric layers separating global interconnect levels are called IMD/intermetal dielectrics or ILD/interlevel dielectrics. Vias connect interconnects through these layers.  These components are part of the metallization/backend/BEOL.

VLSI technology moving to lower technology nodes. Device dimensions of interconnects scales down, by a factor called as ‘scaling factor (S)’. This scaling factor is an integer.  The resistance, capacitance and inductance are affected by scaling. 

Chip surface doesn't have enough space for all connections, so vertical interconnects are built. Number of metal layer increases with IC complexity. Aluminum interconnects were used as the standard for a long time in chip-making. In the late 1990s, chip-makers switched to Cu because it conducts electricity better than Al. Cu interconnects improved IC performance and can match transistor scaling.

VLSI Interconnects: Local & Global

There are two major types of interconnects Interconnects , Local & Global. Local interconnects are the first/lowest level of interconnects. They connect gates, sources and drains in MOS technology and emitters, bases, and collectors in bipolar technology. Local interconnects are small and short.  Poly Si, Silicide, TiN, W (Tungsten) can act as local interconnect. Local interconnects can afford to have higher resistivities since they do not travel very long distances. But they must also be able to withstand higher processing temperatures. Global interconnects are usually made of Al. They are above the local interconnect level.   Global interconnects are thick, long, and widely spaced. They often travel over large distances, between different devices and different parts of the circuit, and therefore are always metals with lower resistivities.

Desirable/Expected VLSI Interconnect

Ideally we assume, wire only connects functional elements and does not affect design performance. Voltage changes at one end and appears at its other end without any delay, i.e. wire is an equal potential region. 

Materials properties that are desirable in a metal interconnect material are :

i.   Low electrical resistivity

ii.  Low capacitance i.e. low dielectric constant.

iii. Low capacitance i.e. low dielectric constant (for low RC delay, cross talk, power loss)

iv. High electro-migration resistance.

v.  Ease of deposition of thin films of the material.

vi. Ability to withstand the chemicals and high temperatures required in the fabrication process.

vii. Stable contact structures. 

viii. Adherence to insulating films (SiO2 )

ix.  Low internal stress, surface roughness

x.   Easily etched using plasma processes

xi.  Compatibility with all other semiconductor processes

xii. Low cost

Real/Fabricated VLSI Interconnects

Now let's try to understand how fabricated interconnects behave in real world. Interconnects have a resistance, capacitance, and inductance per unit length.

Wiring of IC forms a complex geometry that introduces:

i. Capacitive Parasitics,

ii. Resistive Parasitics

iii. Inductive Parasitics.

Parasitics have impact on circuit behavior, such as : 

i. increases propagation delay causing a drop in performance.

ii. impact on the energy dissipation and the power distribution.

iii. Introduces extra noise resulting in the reliability of the circuit.

Modeling of the wire capacitance(s) is a not a trivial task. It require physical understanding of the device structure electrical understanding of the circuit and  mathematical understanding of models used to describe capacitance.  There are two types of capacitance occurring:

1. Parallel plate Capacitance ; 2. Fringe Capacitance.

Capacitance of a wire is a function of shape, distance to surrounding wires and substrate. The resistance of a wire is proportional to its length L and inversely proportional to its cross- section A. Inductance in interconnect is represented by voltage drop due to rate of change of current with time.

Parasitic Extraction :

Parasitic extraction is to calculate the parasitics of wires and create an analog model of the circuit. Extracted parasitics are included in timing, power analysis to get more realistic result. Standard Parasitic Exchange Format (SPEF) is an IEEE standard for representing parasitic data of wires in a chip in ASCII format.

Interconnect Parasitics in VLSI :

1. Resistance :

The resistance of a wire is : 

Where L= length, A= cross section of the wire, H= Height

and W= Width of the wire,

= resistivity of the metal

2. Inductance :

The inductance of a section of a circuit states that a changing current passing through an inductor generates a voltage drop.

An important source of parasitic inductance is due to bonding wires and chip packages.

3. Capacitance :

1. Parallel Plate Capacitance :

where W and L are respectively the width and length of the wire, and tdi and εdi represent the thickness of the dielectric layer and its permittivity.

2. Fringe/Fringing Capacitance :

The capacitance between the side-walls of the wires and the substrate. W,L are respectively the width,length of wire.

3. Total wire Capacitance :

Back End Of Line(BEOL)

The Back-End-of-Line (BEOL) is the portion of IC fabrication where the wiring is done through Metalization/Vias including Dielectric separators among various metal layers.

BEOL steps are like :

1. Silicidation of Poly-Silicon and Source/Drain Diffusion.

2. Then adding a Pre-Metal-Dielectric(PMD) & CMP processing it.

3. Make holes in PMD & create contact through It.

4. Add metal layer 1.

5. Then add dielectric layer a.k.a Inter-Metal Dielectric (IMD).

6. Through CVD make vias through IMD to connect lower and higher metal layer .

7. Carry on last three steps until all the metal layers as per the tech node are done.

8. Add final passivation layer to protect the chip.

BEOL Corners : C Worst, C Best, Cc Worst, RC Best, Rc Worst.

Resistance & Reliability :

Electromigration:

A chip may go above 100 Degree Celsius during practical operation. High frequency power loss & consequent heat dissipation contributes in increased temperature. Rise in temperature enhances solid-state metal ion diffusion. Electro-migration is caused by scattering of the moving electrons with the ions, i.e., by momentum transfer between electrons and ions in metal interconnects. This ion-electron interaction is sometimes referred to as "electron wind.” This causes the wire to break or to short circuit to another wire. Such situation void in interconnects can leads to open circuit i.e chip failure. EM is one of the most menacing and persistent threat to interconnect reliability.

Ohmic Voltage Drop:

Current flowing through a real wire results in an ohmic voltage drop that degrades the signal levels. The affected value of the voltage reduces noise margins and changes the logic levels as a function of the distance from the supply terminals. IR drops on the supply network also impact the performance of the system. A small drop in the supply voltage may cause a significant increase in delay. 

RC Delay :

Signal doesn’t travel instantaneously in wires and the delay of a wire grows quadratically with its length. The signal delay of long wires is dominated by the RC effect. This is becoming even bigger problem in modern technologies. This leads to a siuation that take multiple clock cycles to get a signal from one side of a chip to its opposite end.

Capacitance & Reliability :

Capacitive Coupling:

In real world of ICs, each wire is coupled to both grounded substrate and also to the neighboring wires on the same layer and on adjacent layers. Some capacitive components connect to other wires with dynamically varying voltage levels. Such variable/floating capacitors causes cross-talk and a negative effect to the circuit.  Delay in the signal transmission through wire is proportional to the capacitance charged.  More capacitance means more dynamic power.   Coupling capacitance is an increasing source of noise and makes delay estimation hard.  

Methods to Reduce Interconnect Capacitance : 

 i. Use of low k dielectric which reduces permittivity and hence the capacitance. 

ii. Increase the spacing between the wires (Not always possible).

iii. Separate the two signals with a power or ground line (acting as shield). 

iv. Use minimum wire width wherever possible. (Increase resistance)

Crosstalk :

It occurs due to unwanted coupling from a neighboring signal wire to a network node. The resulting disturbance acts as a noise source. Capacitive cross talk is the dominant effect at current switching speeds. The potential impact of capacitive crosstalk is influenced by the impedance of the line under examination. The design functionality and its performance can be limited by noise. The noise impact can limit the frequency of operation of the design and it can also cause functional failures. Cross talk may lead to setup or hold violation. 

Propagation Delay :

Capacitive cross talk may result in a data-dependent variation of the propagation delay. Coupling capacitance is a large fraction of the overall capacitance in the dense wire structures of advanced technology nodes. This increase in capacitance is substantial, and has a major impact on the propagation delay of the circuit.

Inductance and Reliability

L(di/dt) Voltage Drop :

During each switching action, a transient current is sourced from or sunk into the supply rails to charge/discharge) the circuit capacitances. Both Vdd and Vss connections are routed to the external supplies through bonding wires and package pins and possess a non ignorable series inductance. Change in the transient current creates leads to large current surges.

Transmission Line Effects:

When an interconnect becomes sufficiently long or when the circuits become sufficiently fast, the inductance of the wire starts to dominate the delay behavior and transmission line effects become significant.

Impact of Scaling :

Wires are subdivided into short and long wires. Short wires are typically used for local communication between gates.  Long wires are used for long range communication at the different corners of of the IC.

Watch the video lecture here :

 

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Cross-talk in VLSI PD : Interconnect Series - 4

In this article we will discuss about Signal Integrity and Cross-talk. Once completed you will be able to answer below questions:

1. What is signal integrity and what are common signal integrity issues?

2. What is cross talk and how it impact signal integrity?

3. Different types of  glitch : Rise glitch, Fall glitch, Overshoot Glitch, undershoot Glitch.

4. Different types of cross talk delays : Positive and Negative delay.

5. Impact of delay on set up and hold timing

6. How to minimize impact of cross talk? 

Signal Integrity in Physical Design:

In digital electronics a stream of binary data is transmitted as signal and it represented as voltage (or current) waveform. All signals are subject to noise, distortion and loss. Signal Integrity is the measure of quality of a signal as it travels from one point to another point. Signal integrity is crucial as it ensures whether the data transmission is accurate, reliable, and immune to unwanted effects such as noise, distortion, and reflections. If the signal faces above mentioned unwanted continuously, it can lead to erroneous data transmission. 

The signal integrity mainly deals with : 1. timing and 2. quality of the signal. Signal integrity is both an interconnect level problem, as well as a systems-level problem. Any design have some signal integrity problem and they generally do not interfere with the functionality of the system by creating excessive, until the system deals with high frequency signals.

Common Signal Integrity Issues in PD : 

In a digital system SI analysis are done in three levels :

1) logic level , 2) circuit level , 3) EM field level.

In logic level analysis Signal Integrity issues can be easily identified. Circuit level Signal Integrity analysis is based on interconnect modeling. Here we try to model a piece of interconnect including resistive, capacitive and inductive effect. At Electro-Magnetic level, most of the signal integrity issues are reflection, cross-talk, ground bounce etc. Circuit level analysis obtain a good SI solutions at low frequency whereas for state-of-art ICs with small dimension and high operating frequency EM level analysis is more accurate to describe the effects. SPICE tools are used to check SI in nodal analysis and they solve voltage and current in the RLC circuit.

Here are the major issues concerning signal integrity:

1. Cross-talk Delay

2. Cross-talk Noise

3. Ringing & Ground bounce

4. IR (voltage) drop in power lines

5. Electro - migration

6. Manufacturing-related issues that if not addressed can lead to chip failure (Antenna Effect)

Cross-Talk :

Cross-talk is the undesirable electrical interaction between two or more adjacent nets due to capacitive coupling. Switching of the signal in one net (aggressor) can interfere neighboring net (victim)due to coupling capacitance this is called cross talk. Aggressor is a net which creates impact on the other net. Victim is a net which is impacted by aggressor. 

Cross-talk has two effects : Cross-talk Noise & Cross-talk Delay

Cross-talk Noise/Cross-talk Glitch:

-Signal transition in aggressor causes a noise bump or glitch on victim net. This in known as cross-talk noise.

-Cross-talk noise/glitch/bump occurs when aggressor net switches and the victim nets remain in a steady state.

Cross-talk Delay/Cross-talk Delta Delay:

-Signal transition in aggressor create delay in the output transition of victim. This is known as cross-talk delay.

-Cross-talk delay occurs when both aggressor and victim nets switch together.

Classification : Rise & Fall Glitch

Lets now discuss about Rise and Fall Glitch.

Rise Glitch : Victim net is at a steady low, aggressor net is switching low to high. 

1. G1 I/P→ 1to 0 and node A , 0→ 1.

2. Node A, 0 →1 , Cm starts to get charged.

3. O/P of G3 and Node V at 0.

4. Leakage current through Cm create a rise in voltage glitch at V.

Fall Glitch : Victim net is at a steady high, aggressor net is switching high to low.

1. G1 I/P→ 0 to 1 and node A , 1→ 0.

2. O/P of G3 and Node V at 1.

3. Node A switches from 1to 0 and Nove V at 1.

4. Leakage current Cm flows from V to A and

create fall in potential at V.

Classification :Over & Under Shoot Glitch

Over Shoot Glitch : Victim net voltage is at steady high and aggressor net is switching from
low to high, induces overshoot glitch by taking the victim net voltage above its steady high.

Under Shoot Glitch : Victim net voltage is at steady low and aggressor net is switching from

high to low, induces undershoot glitch by taking the victim net voltage below its steady low.

What Impacts Glitch?

Not all glitches are considered unsafe for circuit operation. Safe/Unsafe decided by glitch height.

Glitch Height : Magnitude or height of the glitch is determined by few factors. Such as:

1. Value of Coupling capacitance :

Magnitude of glitch would be higher if the coupling capacitance value is higher.

2.  Slew of the aggressor net:

If the output drive strength of the cell that is driving the aggressor net is high, slew of the aggressor net is faster. The faster slew of the aggressor net results in high magnitude of glitch.

3. Drive strength of aggressor and victim net:

If driving strength of aggressor net is high the magnitude of the glitch will be higher, whereas if driving strength of the victim net is higher it is not easy to influence it.

4. Grounded Capacitance :

If victim net grounded capacitance is small then the magnitude of glitch will be large.

Multiple Aggressor :

When multiple aggressor are present and they switch concurrently the impact on victim net is get added.Concurrent switching is an ideal case. In reality more than one aggressor net can switch together or their switching action can share same time window. So the impact on victim net depends on the contribution of each aggressor node on that victim net for a time window.

Range of Safe & Unsafe Glitch :

- Safe Glitch : Has no effect on logic state of victim net.

- Glitch height < Noise Margin Low (NML), a safe glitch.

- Glitch height > Noise Margin High (NMH), a unsafe glitch.

- NML < Glitch Height < NMH , an unpredictable case.

- Noise margin is a parameter that determines the allowable

noise voltage on the I/P without affecting O/P.

- Noise margin/immunity expressed in terms of NML, NMH.

- NMl = Vil – Vol (difference in magnitude between the max.

LOW output voltage of the driving gate and the max. input

LOW voltage recognized by the driven gate).

- NMh = Voh - Vih(difference in magnitude between the min.

HIGH output voltage of the driving gate and the min. input

HIGH voltage recognized by the receiving gate)

Cross-talk Delay Basics:

Crosstalk delay occurs when both aggressor and victim net switching. It may leads upto setup and hold timing violation. Crosstalk delay increase or decrease the delay of a cell depending upon the switching direction of aggressor and victim nets. There are two types of cross-talk delay: Negative Crosstalk Delay & Positive Crosstalk Delay

Negative Cross-talk Delay : 

Aggressor and victim nets switch in the same direction :

1) Both net switches from low to high

2) If aggressor has higher driving strength, transition will happen faster.

3)A potential difference from node A to V will be developed.

4) Node A will try to pull up the victim node.

5) Transition of the victim node will have a bump.

6) Victim net will reach from 0 to 1 earlier and transition time will decrease.

7)Cross-talk will be decrease the delay by Δ and the new delay will be (D – Δ).

Positive Cross-talk  Delay : 

Aggressor and victim nets switch in the opposite direction :

1) Aggressor net and node A switches from 0→ 1.

2) Victim net or node V switches from 1→ 0.

3) There will be a potential difference from node A to V.

4) Node A will try to pull up node V.

5) There will be a bump in victim net waveform.

6) Transition of the victim node will have a bump.

7) Victim net will take longer time to reach from 1 to 0.

8) Transition time will increase.

9)Cross-talk will be increase the delay by Δ and the new delay will be (D + Δ).

Effects of Cross-talk Delay:

1. Effect on clock tree: Cross talk can unbalance a balanced clock tree. Cross-talk delay can change the latency of balanced path and the clock tree become unbalanced.

2. Effect on Setup timing:

For setup timing data should reach the capture flop before the required time of capture flop. Setup time violation occurs due to increase of delay in data path/launch clock path, decrease in delay on the capture clock path

3. Effect on Hold timing:

For hold timing data must be stable for minimum amount of time after the clock's active edge. Hold time violation occurs due to decrease of delay in data path, launch clock
and increase of delay in the capture clock.

Cross-talk & RT Level Estimation :

Each design stage has its own models for cross-talk.

Trade-offs exist between the accuracy and complexity

of these different models. The cost involved in detecting errors and correcting them increases by a factor of 10 between each abstraction level as we move top-down in the ASIC design flow. Detecting cross-talk sensitivity at the gate-level is 10 times more expensive than detecting it at the RT-level. Some low level parameters have direct impact on cross-talknoise problem and those cannot be accurately determined at higher abstraction levels. Such parameters are :

1. The positions of the modules, relative to one another(can  be determined after floor-planning )

2. The route of each wire (can be determined after floor planning)

3. The aggressors of a given wire in both the horizontal and the vertical planes (can be determined after floor planning)

Thus, high-level cross-talk estimation in includes mathematical and statistical process.

Mitigation Methods of Cross Talk: 

1. Increasing the space between aggressor and victim net:

If the distance between aggressor and victim nets is increased, the mutual inductance between them will decrease.

2. Insertion of Shielding Net :

Inserting a net which is connected to Vss/Vdd between critical aggressor and victim net is a method. This new net in between works as shield, and this process is known as shielding. Process of shielding stops direct coupling between aggressor and victim net and since the shielding net remain at constant potential chances of cross-talk is completely waived off.

3. Upgrading drive strength of victim cell :

If we upgrade the driving strength of victim cell, it will not be easy to change its logic state.

4. Downgrading drive strength of aggressor cell :

If we downgrade the driving strength of aggressor cell, its impact on victim cell will decrease.

5. Buffer insertion:

Insertion of buffer effectively boost the victim net strength.

6. Guard Ring :

Guard ring in the substrate use to shield the analog circuitry from digital noise.

Find the video lecture here: 

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