Multi Patterning Lithography : VLSI Milestone , Episode-7

In the article, an array of pivotal topics within the realm of VLSI have been meticulously explored. The discourse embarks on a journey through the significant milestones achieved in VLSI, particularly delving into the intricate domain of Multiple Patterning techniques. Within this realm, a thorough investigation into Lithography is conducted, unraveling its various types and shedding light on the indispensable concept of Multi-Patterning. The imperative necessity for Multi-Patterning in modern semiconductor fabrication processes is scrutinized, elucidating its role in overcoming the constraints posed by traditional lithographic methods. Furthermore, the discourse navigates through the complexities of Phase Shift Mask and Optical Proximity Correction, unveiling their critical roles in enhancing lithographic precision. Moreover, the session ventures into the intricacies of Layout Decomposition, Double Patterning, and even explores advanced techniques like Triple and Quadruple Patterning, illuminating the evolving landscape of VLSI fabrication methodologies.

VLSI Milestone & Multiple Patterning:

Moore’s law has been driving and guiding force for last few decades for enhancement of device performance. As minimum feature size has reduced, CMOS process has been greatly challenged by patterning technique of such miniature device dimension. Due to the fundamental optical resolution limit, the 193nm immersion lithography can only achieve the minimum pitch about 80nm using single exposure. To continue the technology scaling in 22nm, 14nm, and beyond with the 193nm lithography, multiple patterning technologies have been developed to obtain finer pitches. Multi-patterning became a necessary step as next-generation extreme-ultraviolet (EUV) lithography tools were not yet ready for production. 

There are two main types of multiple patterning lithography :

(i) based on repeated process,

(ii) based on self-aligned spacer process.

Lithography:

Lithography is the process of transferring patterns of geometric shapes in a mask to a thin layer of radiation sensitive material/resist covering the surface of a semiconductor wafer.

An IC fabrication facility requires a clean room, particularly during lithography process. Dust particles settling on  semiconductor wafers and lithographic masks can cause defects in the devices. Performance of a lithographic exposure is determined by three parameters: (i) resolution, (ii) registration, (iii) throughput.

 Resolution is defined to be the minimum feature dimension that can be transferred with high fidelity to a resist film on a semiconductor wafer. Registration is a measure of how accurately patterns on successive masks can be aligned or overlaid with respect to previously defined patterns on the same wafer. Throughput is the number of wafers that can be exposed per hour for a given mask level and is thus a measure of the efficiency of the lithographic process

Different Types of Lithography:

Optical Lithography : Majority of lithographic equipment for ICfabrication is optical equipment using light in the ultraviolet range of the EM spectrum.

(a) DUVL : Uses controlled 254–193-nm light to create pattern.

(b) EUVL : Uses 13.5 nm light to create intricate patterns on silicon wafers. EUVL wavelength is close to X-ray. EUV lithography reduces the number of mask count, although more expensive than other systems for microchip lithography.

X-ray lithography: Uses X-rays, X-ray sensitive special resist, a mask composed of an X-ray absorbing material

patterned on a thin membrane that is X-ray transparent, often made of low atomic number elements like Si/B.

Ion Lithography : Ion lithography can achieve higher resolution than optical, x-ray, or electron beam

lithographic techniques because ions undergo no diffraction and scatter much less than electrons.

E- Beam Lithography (EBL) : Direct writing lithographic process. Uses a focused beam of electrons to form patterns. E-beam lithography is not suitable for high-volume manufacturing because of its limited throughput.

Depending on exposure method 3 types of printing are there : 

(i) contact printing

(ii)proximity printing 

(iii) projection printing

What is Multi-Patterning?

A class of technologies developed for photo-lithography to enhance the feature density. A single lithographic exposure may not be  enough to provide sufficient resolution. Multiple patterning is a technique that overcomes the lithographic limitations in the chip-manufacturing process. Single exposure, 193nm wavelength lithography reached its physical limit at 40nm half-pitch. MP enables chipmakers to image IC designs at 20nm and below.

There are two main categories of Multi Patterning: 

(i) pitch splitting and (ii) spacer.

Pitch splitting includes Double and Triple Patterning.

Spacer involves self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP).

Why Multi-Patterning is Required?

Rayleigh criterion specifies the minimum separation between two light sources that may be resolved into distinct objects. Critical dimension or resolution is defined as :

Feature size is constantly dropping to lower value.  CD can be reduced by :                                                                

1. Increasing NA : NA cannot be increased beyond 0.93. It will reduce the depth of focus and sharpness of the image printed become less

2.Decreasing k1 : Reducing k1 is a good option. In single patterning k1 is restricted to a minimum of 0.25 and cannot go beyond that . Using multiple patterning decreases k1 from 0.25.

 3.Decreasing λ :  Reducing λ below 193 nm results in a lot of technical issues cost, risk and throughput.

 If a pitch could not be achieved in a single lithography step, the design is split over two lithography layers so that the minimum pitch is relaxed with respect to the target pitch.

In this way the effective k1 of the total process resulting from combination of the two lithography steps can drop below the 0.25 for a single patterning process. The increased pitch size enables higher resolution and better printability.

Phase Shift Mask :

PSM is used to alter the phase of the light passing through some areas of the mask. Phase change modifies the way light is diffracted. As a result defocusing effect reduces. The downside of using phase-shift techniques is that such masks are more difficult and expensive to make.

Optical Proximity Correction:

A photolithography enhancement technique. Used to offset the optical proximity effect. Photomask patterns transferred onto a photoresist under insufficient resolution develop inaccuracies. In OPC, mask geometry is modified to compensate for pattern transfer non-idealities.

Layout Decomposition : 

Splitting one layer into multiple masks. For MPL , one of the most fundamental problems is to decompose the layout into a specific number of masks, such that each mask should be able to manufactured under current lithography.

When there is not enough distance between two patterns, different masks should be used to print them. It is possible that given masks are not enough to print specific features, which results in conflicts. Thus, one basic objective for layout decomposition is to avoid conflicts.

Double Patterning:

Double patterning is a technique used in the lithographic process for sub 30 nm process. This process requires increased mask and lithography costs. DP is an effective way to counter the effects of diffraction in optical lithography. Such situation occurs because the light source has wavelength of 193 nm and the process node is fraction of that.  Diffraction effects makes it difficult to produce accurately defined deep sub-micron patterns using existing lighting sources and conventional masks. Sharp corners and edges become blurs, and some small features on the mask won’t appear on the wafer at all.

Three types of method :

(i) Litho-Etch-Litho-Etch (LELE):

(ii) Litho-Freeze-Litho-Etch (LFLE):

(iii) Spacer/Self Aligned Double Patterning (SADP):

Triple & Quadruple Patterning :

Triple patterning is quite silimilar like double patterning. In this process polygons are partitioned into three masks. Advantage of triple patterning over double is that it is denser. Although use of 3 masks create misalignment. TP refers to the litho-etch-litho-etch-litho-etch (LELELE). LELELE requires three separate lithography and etch steps to define a single layer.  Provides a reduction in pitch, increase in expense because of increased process steps.

Self-aligned quadruple patterning (SAQP) is the most widely available technology used for patterning feature pitches less than 38 nm.  It is already being used to pattern the fins of FinFETs and DRAM. This process allow lines originally drawn 80 nm apart to generate lines which are ultimately 20 nm apart . Able to do high volume lithography compared to EUV , which has 13 nm resolution. SAQP  process steps are shown below.

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Metallization, Cu interconnect, Low-k : VLSI Milestone Episode-6

The article delves into crucial aspects shaping Very Large Scale Integration (VLSI) technology, notably focusing on milestones and advancements in multi-level metalization. The discussion traverses through the intricacies of metalization, particularly emphasizing its multi-level nature and the components integral to its composition. Noteworthy attention is dedicated to exploring interconnect materials, including the prevalent use of aluminum (Al) and the emerging dominance of copper (Cu), delving into their respective reliability factors. The discourse further delves into the intricacies of the single/dual Damascene processes, distinguishing between aluminum and copper interconnects while scrutinizing their comparative advantages. Additionally, the article video provides valuable insights into low-k intermetal dielectrics, elucidating the underlying physics governing their functionality and exploring various materials characterized by low dielectric constants.

VLSI Milestone & Multi Level Metallization:

Moore’s law has been driving and guiding force for last few decades. With progressing node circuit complexity has increased. Reduced dimension has made short channel effect, parasitic effect more severe. To keep up with the pace of scaling, new material, new device structure was found and introduced. Higher package densities and design flexibility was achieved by increasing interconnect layers. To increase circuit performance different materials incorporated at different part of total interconnect network.  Research led us to new inter-metal dielectric layer or low- k dielectric layer.

Metallization:

Conductive films provide electrical interconnection among devices as well as the outside. Three categories : gate, contact and interconnect. 

Polysilicon and Silicide are frequently used for gate connection , Al/Cu are used as contact and second-level interconnection to the outside. In some cases, a multiple-layer structure involving a diffusion barrier is used. Titanium /platinum/ gold or  titanium / palladium / gold is useful in providing reliable connection to external components.

Circuit speed is controlled by the resistance and capacitance of the interconnect.  Metallization is deposited by either physical vapor deposition (PVD) or chemical vapor deposition (CVD).

Desired properties of the metallization for ICs:

1. Low resistivity , easy to form and easy to etch for pattern generation

2. Should be stable in oxidizing ambients and oxidizable

3. Mechanical stability, good adherence, and low stress

4. Surface smoothness

5. Must be stable throughout processes including high temperature sinter, dry/wet oxidation, gettering, passivation, and metallization

6. No reaction with final metals

7. Should not contaminate devices, wafers, or working apparatus

8. Good device characteristics and lifetimes

9. For window contacts - low contact resistance, minimal junction penetration, and low electro-migration

Multi Level Metallization:

RC Time Delay : As technology progresses, Ls decreases. RC delay increases. 

Length of wire must be kept small – Multi Level Metallization

Lower resistivity metal for interconnect wiring – Cu Interconnect

Lower dielectric constant material for the interlayer dielectric - Low-K

Contact Resistance : Low contact resistance to semiconductor device

Immunity to EM : reliable long-term operation

State-of-art ICs have millions of transistors and connecting them all to some voltage and current supply without wires crossing is a real challenge. 3-D network of interconnections is called Multi Level Metallization. Multi-level metallization increases interconnect capacity and reduces resistance and capacitance.

Stretches over several planes and isolated by the insulating dielectric layers. Interconnected by the wiring through the holes in the dielectric planes.

Benefit of Multi Level Metallization:

- Reduced interconnection lengths and reduced RC,

- Higher package densities and design flexibility

Components of Multi Level Metallization:

Components of Multi Level Metalization Circuit are:

(i) Interconnects, 

(ii) Contacts, 

(iii) Vias, 

(iv) Intermetal Dielectric ,

(v) Passivation.

Active devices are electrically connected to each other. They are connected to the outside world through their I/P and O/P on bonding pads. Contact is connection to source, drain or poly. Vias are connections between interconnect levels.   Interconnects are separated from each other by dielectric layers.  Vias connect interconnects through these layers. These components are part of the metallization/backend/BEOL.  Local interconnects are the first/lowest level of interconnects. They are small and short and connect gates, sources and drains. Poly Si, Silicide, TiN, W (Tungsten) can act as local interconnect. Local interconnects can afford to have higher resistivities since they do not travel very long distances. They must be able to withstand higher processing temperatures. Global interconnects are usually made of Al/Cu. They are above the local interconnect level. Global interconnects are thick, long, and widely spaced. They travel longer distances, between different devices and different parts of the circuit, and therefore are always metals with lower resistivities. After completion of metallizationa passivation layer is formed to protect the internal semiconductor devices. The passivation layers are typically formed with deposition of an oxide layer and a nitride layer.

Interconnect Material : Aluminium(Al)

Aluminum interconnects were used as the standard for a long time in chip-making. In the late 1990s, chip-makers switched to Cu.

=>Advantages of Aluminium :

- It is a good conductor

- It can form mechanical bonds with silicon

- It can form low resistance, ohmic contacts with heavily doped n-type and p-type silicon

- Corrision resistant

=>Disadvantages of Aluminium :

- Low melting point

- Junction Spiking

- Electromigration

- Stress migration

=>Junction Spike :

Use of pure aluminum leads to a diffusion of siliconinto the metal. Si reacts with the metallization at only 200–250 °C. This diffusion of Si causes cavities at the interface of both materials which are then filled by Al. This leads to spikes which can cause short circuits if they reach through the doped regions into the silicon crystal beneath. Size of these spikes depends on the temperature at  which the Al was deposited. To avoid spikes a deep ion implantation can be introduced at the location of the vias. Thus the spikes do not reach into the substrate.  An alloy of aluminum and silicon can be used (silicon 1–2 %). Since Al now already contains silicon there will be no diffusion out of the substrate. A barrier of different materials such as titanium, titan nitride or tungsten is deposited as barrier layer.

=>Electromigration:

Electro-migration is the movement of atoms in a metal film due to momentum transfer from the electron carrying the current. Under high current density condition metal atom movement creates void in some region and metal pileup or hillock in the other regions.  As a result either open ckt. or short ckt. happens in interconnect networking. A common practice to prevent Em is to use an i.e. alloying with copper (Al with 0.5%Cu).

=>Stress Migration:

Due to difference between coefficient of thermal expansion for Al and Si. At high temperature compressive stress get created in Al. Movement of Al occurs along grain boundaries. Whole grains of Al pushed upward forming hillocks. Tensile stress creates voids, crack i.e. electrical open. Compressive stress creates hillocks i.e electrical shorts.  Rough surface topography making lithography and etch difficult.

Interconnect Material : Copper(Cu)

Use of diffusion barriers and adhesion promoters :

Cu has poor adhesion properties. An adhesive material is required which will provide stability across interface. Silicides such as TiSi2 can be used as adhesion promoter. TiSi2 doesn’t have good barrier properties. To stop reaction between metals (W, Al etc) and Si or between two layers a barrier layer is used. TiN has contact resistance higher barrier than TiSi2. Bilayer structure of TiSi2 /TiN is used as adhesion promoter and diffusion barrier.

Unlike Al metallization, Cu cannot be easily patterned by reactive ion etching (RIE). Hence, to fabricate Cu interconnects, a different process flow which is called “damascene” process has been developed, including “single damascene” and “dual damascene” processes.

Single/Dual Damascene Process :

In Single Damascene process first inter layer dielectric layer is deposited and via is etched out. Next via is filled with Cu. Excess Cu is removed by Chemical mechanical Polishing (CMP). After that trench is etched out from ILD and filled with Cu. Excess Cu again removed using CMP. 

In Dual Damascene process inter layer dielectric layer is deposited and after that trench and via both are etched. After that Cu is filled and excess Cu is removed using CMP. In

Dual Damascene process less step and time is required. Depending on whether trench or Via which one is etched earlier the process is named as (i) Via first or (ii) Trench first.

Low K Inter Metal Dielectric:

Lower-k dielectrics are grouped as ,(i) Ultralow-k (k < 2.2-2.4) or  (ii) low-k (2.4 < k < 3.5). These materials can be deposited either by a spin-on route (spin-on dielectrics or SODs) or by a chemical vapor deposition (CVD) or plasma-enhanced PECVD technique. Their final properties are influenced by both the deposition method and post deposition treatment such as anneals or chemical treatments. 

Physics of Low-K Dielectric:

Dielectric constant k is also also called relative permittivity εr. K =(Permittivity of a substance/ Permittivity of free space) A material having polar components, has an increased dielectric constant. These polar chemical bonds are represented as electric dipoles. When external electric field applied, the dipoles align with the field. Electric field of every dipole is added to the external field. A capacitor with a dielectric medium of higher k will hold more electric charge at the same applied voltage. Therefore C will be higher.

Reducing K:

- 2 possible ways :

(i) reducing dipole strength - lower polarizability

(ii) reducing number of dipoles - lower density

- The two methods can be combined to achieve

even lower k values.

Si-O bonds replaced with less polar Si-F/Si-C bonds.

Using virtually all nonpolar bonds: C-C/C-H.

Density of a material can be reduced increasing free

volume through rearranging the material structure or introducing porosity.  Porosity can be constitutive/subtractive.

Constitutive porosity refers to the selforganization of a material. After manufacturing, such a material is porous without any additional treatment.  Subtractive porosity involves selective removal of part of the material.

This can be achieved via an artificially added ingredient .

Different Low-K Material:

Classification of Low-K material:

(i)Si - containing , (ii) non-Si-containing.

2 types of Si-containing materials:

(i) silica-based , (ii) SSQ-based. 

To reduce the k value of silica, some oxygen atoms

are replaced with F, C, or CH3.

Addition of CH3 introduces less polar bonds and

also creates additional free volume.

The first low-k materials were F- or C-doped SiO2.

In SSQ , Si and O atoms are arranged in a form of cube.

This creates free volume in the center of the cube,

decreasing the material’s density and K value. The cubes can be connected to each other through

oxygen atoms.

HSSQ - some cube corners are terminated by hydrogen

MSSQ – some some cube corners are methyl group.

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Performance Boost by FinFET : VLSI Milestone Episode-5

VLSI Milestone & FinFET

Scaling degrades perfomance of deep submicron MOSFET devices. Vd controls the channel and Vg losses control over channel.  Vg is unable to shut off the channel completely in the off-mode of operation, which leads to an increased Ioff between drain and Source. Multiple-gate field-effect transistors (MGFETs), emerged as an alternative to planar MOSFETs. MGFETs demonstrate better control over channel and MOSFET performance. Among all MGFETs, FinFETs (a type of DGFET) and Trigate FETs (another popular MGFET with three gates) have emerged as the most desirable alternatives to MOSFETs due to their simple structures and ease of fabrication.

Leakage Current and Novel Structures:

Gate cannot control leakage path far away from gate. SOI MOS structure reduce leakage and chance of latch up.  Addition of another gate can increase control over channel. The main idea of a DG MOSFET is to control the Si channel more efficiently compared to planar MOSFET. Si channel width is usually kept small and voltage is applied on both sides of channel. Such a structure and operation effectively suppress short channel effects and leads to higher currents as compared with a MOSFET having only one gate.

Evolution of Different Multi Gate FET:

What is FinFET?

A multigate non-planar Field Effect Transistor. Channel is wrapped with gate from two/three sides.  FinFET is Fin-Shaped-FET. Fin is a body part of fish which stick out of its body. A Silicon Fin forms its body. The channel of the FinFET is vertical. 

Lg = gate length , Tsi = fin thickness , Hfin = fin height

Can be built over bulk silicon or SOI wafer.

For double-gate: W = 2 ∙ Hfin ; For tri-gate: W = 2 ∙ Hfin + T

Different Types of FinFET: 

Two types of Gate design :  

    i. Double Gate FinFET

    ii. Triple Gate FinFET

Two types of gate connection : 

 i. Shorted Gate FinFET (SGFinFET) : 3 terminal device. 

Front and back gate are physically connected/shorted. Electrostatics of channel is controlled by both gates together.

ii. Independent Gate FinFET (IGFinFET) : 4 terminal device. 

Gates are isolated. Different voltages can be applied to gates. This flexibility is very useful.

Two types of Wafer : 

   i.  Bulk FinFET

   ii. SOI FinFET

Planar MOSFET vs FinFET :

FDSOI MOSFET vs FinFET

Bulk FinFET vs SOI FinFET

Corner Effect:

Corner Effect : 

Charge accumulation at corners or areas with higher curvature are higher (basic Physics). So electric field at corners are higher. Same rule follows for FinFET. Charge accumulation and electric field higher at corners. High channel doping create premature inversion at the corners due to charge accumulation. Electric field coupling in device corners results in lower threshold voltage of corner regions. Corners are turned on earlier (at lower gate voltages) than the other parts of the channel. This doesn’t exist in the other parts of thesilicon/silicon-dioxide interface. This means that different regions of the transistor with high electron density are activated at different gate voltages. This premature inversion at the corners of the triple gate FinFET degrades the sub-threshold characteristics of the FinFET which results in higher off state leakage. The corner effects must be suppressed to avoid leakage currents. There are various techniques available toeliminate the corner effects, such as, reduction in doping concentration in channel, and corner rounding etc.

Process Variations :

FinFETs suffer from process variations. Due to small dimensions and lithographic limitations, FinFETs are subjected to physical fluctuations, like variatioins in gate length , fin- thickness , gate-oxide thickness and gate underlap . Gate oxide is on the etched sidewall of the fin, and may suffer from nonuniformity. The degree of nonuniformity depends on the line-edge roughness (LER) of the fin.

FinFET Fabrication Flow – 1 & 2

Wafer Preparation: 

Cleaning of wafer. Base is a lightly p-doped substrate with a SiN (silicon nitride) hard mask and a patterned resist layer on top .

Fin etching : 

Highly anisotropic etch process is used. The etch process is time based as there is no stop layer on a bulk wafer. In 22 nm process the width of the fins might be 10 to 15 nm, whereas the height would must be twice of that or more.

Oxide deposition : 

To isolate the fins from each other a oxide deposition is

done.

Planarisation : 

Planarisation is done. This is the process to increase the

smoothness or planarity of a wafer through process like CMP.

Recess etch : 

Another etch process is needed to recess the oxide film to form a lateral isolation of the fins.

Gate oxide :

Gate oxide is  deposited on top of the fins by thermal oxidation to isolate the channel from the gate elctrode. Since the fins

are still connected underneath the oxide, a high- dose angled implant at the base of the fin creates a dopant junction and

completes the isolation (not illstrated).

Gate Formation : 

A highly n+ doped poly silicon layer is deposited on top of the fins, thus up to three gates are wrapped around the channel:

one on each side of the fin, and - depending on the thickness of the gate oxide on top - a third gate above.

Since there is an oxide layer on an SOI wafer, the channels are isolated from each other anyway. In addition the etch process of the fins is simplified as the process can be stopped on the oxide easily.

FinFET Advantages:

• Better control over the channel
• Suppressed short-channel effects
• Lower static leakage current
• Faster switching speed
• Higher drain current (More drive-current per footprint)
• Lower switching voltage
• Low power consumption

FinFET Disadvantages:

• Self-Heating Effect
• Quantized device-width. It is impossible to make fractions of the fins, whereby designers can only specify the devices’ dimensions in multiples of whole fins.
• Higher parasitics due to 3-D profile
• Very high capacitances
• Corner effect
• High fabrication cost

Big Houses Who Work With FinFET Technology :

Products in which FinFEt Technology is used:

Technology Nodes :

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