In this insightful article, we delve into several key aspects within the realm of VLSI technology, focusing primarily on the groundbreaking concept of Strained Silicon as a channel material. Our discussion encapsulates the significance of Strained Silicon, positioning it as a pivotal milestone in the evolution of VLSI. Throughout the video, we unravel the intricate details surrounding Strained Silicon, exploring fundamental questions such as the nature of SiGe (Silicon Germanium) and the application of strain in Silicon. The discourse extends to a comprehensive examination of the band structure of Silicon, shedding light on the nuanced effects of biaxial tensile strain and compressive strain. By addressing these critical facets, we aim to provide a thorough and elucidating overview of the multifaceted world of VLSI technology and its transformative Strained Silicon component.
VLSI Milestone & Strained -Si:
From 90 nm technologies, the performance boost by method of MOSFET dimension scaling started to diminish. MOSFET scaling resulted in several physical limitations. Higher body doping leads to lower carrier mobility, higher junction capacitance, increased junction leakage Thinner gate dielectric leads to higher gate leakage Strained Silicon channel has been introduced as technology booster. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels and drive current, respectively, at the same supply voltage and gate oxide thickness. Tensile and compressive strain applied to channel. Strain changes lattice constant and energy band structure of silicon.
What is Strain Si?
Strained Silicon is literally Silicon which is strained. Strain is induced using different mechanism. In Strained-Si atoms are stretched beyond their normal inter-atomic istance. Advantage of s-Si relies in its ability to fundamentally alter the band structure in ways that increase the effective mobility. The basic idea in strained Si CMOS is to modify the carrier transport properties of Si by introducing strain in order to improve performance of MOSFETs. Mobility improvement in strained silicon takes place mainly due to the reduction of the carrier conductivity effective mass and the reduction in the inter-valley phonon scattering rates. Semiconductor with smaller lattice constant than substrate leads to compressive stain on top layer. Semiconductor with larger lattice constant than substrate leads to tensile strain on top layer.
What is SiGe?
SiGe is an alloy with any molar ratio of silicon and germanium, i.e. with a molecular formula of the form Si1−xGex. Used as a semiconductor material in integrated circuits (ICs) as a strain-inducing layer for CMOS transistors. The biaxial tensile strain in the strained Si layer on relaxed SiGe can be tailored by the Ge content.
How strain is applied in Si?
Two types of strain : Tensile and Compressive strain. Two direction of strain : Biaxial and Uniaxial Strain.
Biaxial strain/Global Strain :
Introduced by epitaxial growth of Si and SiGe layers. The strain is induced by the lattice mismatch between Si and SiGe.
Advantages : Uniformly strained layers obtained. Can be implemented with standard CMOS process with minimal modification.
Disadvantages :Limited improvement of PMOS transistor performances, occurrence of defects and dislocations at the boundary surfaces, increased production costs.
Uniaxial /Local Strain :
Introduction of local structures and materials cause strain in the channel of transistors. This is local/uniaxial strain.
In pMOS the source and drain are formed by epitaxial SiGe which introduce uniaxial compression in the channel area . A tensile capping layer in nMOS creates uniaxial strain.
Band Structure of Silicon:
Each energy level of silicon is composed of six equal energy valleys in three dimensions. In inversion layers, these six valleys are split into two fold out of plane valleys located at the kz axes (001) direction and four fold in-plane valleys in kx (010) direction and ky axes (100) direction. The electrons in all these conduction valleys have transverse mass (mt =0.19m 0 ) and longitudinal mass (m l = 0.916m 0 ). Clearly ml > mt .
In the two fold valleys, the electrons have transverse mass parallel to the MOSFET Si/SiO2 interface and longitudinal mass perpendicular to the interface.
On the other hand, in four fold valleys, the electrons have transverse mass perpendicular to the MOSFET Si/SiO 2 interface and longitudinal mass parallel to the interface. There are three valence band subband : HH,LH and SO.
Impact of Biaxial Tensile Strain :
With tensile strain, two out of plane (∆ 2 )valley move lower and the ∆ 4 valleys move upward energitically. This band alteration gives an alternate lower site for electrons to reside i.e. ∆ 2 valleys. Value of mt in the lower energy valleys ∆ 2 is lesser than the ∆ 4 valleys in the direction parallel to the interface suitable for the flow of electrons from the source to drain. Inter-valley phonon scattering between the lower and upper states is decresed. Due to this, the electron mobility increases. With strain, valence sub-bands splits and their shapes changes. HH and LH bands split and move away and SO hole subband move downward further. Both in-plane and out-of-plane hole mobility is improved mainly due to the reduced inter-band and intra-band scatterings.
Impact of Compressive Strain:
Both biaxial and Uniaxial stresses have similar effect on the conduction band structure whereas the effects on the valance band are much different. Hence, the mobility gain is similar for uniaxial and biaxial strain, as it results from the splitting of the six-fold degenerate conduction band valleys for both types of stress.
The uniaxial strain has much more significant advantageous effect on the valance band relative to biaxial stress.
In this extensive article, we thoroughly explore various essential aspects related to VLSI technology and SOI MOSFET. The discussion commences with an introduction, providing viewers with an initial overview, followed by a helpful chapter index for easy navigation through subsequent topics. The focus then shifts to VLSI milestones and the significance of SOI MOSFET. A detailed exploration of SOI follows, including an explanation of what SOI is and an in-depth examination of its fabrication process in three parts. The video proceeds to unravel the reasons behind VLSI's adoption of SOI, contrasting it with the drawbacks of Bulk MOSFET. Further insights into the advantages of SOI are provided, followed by an intricate analysis of the performance of SOI MOSFET. Specific attention is given to the phenomena of Kink Effect and strategies for reducing Floating Body Effect. The video concludes with a comparative exploration of FDSOI vs PDSOI, offering viewers a comprehensive understanding of the intricate aspects of SOI MOSFET technology in the field of VLSI.
VLSI Milestone & SOI MOSFET
Moore's law has been the main driving force for last few decades. Device dimension reduced and performance got boost. Down scaling has resulted in short channel effect. New device structure like SOI has been introduced. Global Foundry has developed SOI solutions for high-growth, high-volume wireless and WiFi markets. FD-SOI is a suitable technology for new standards for IoT, automotive and mobile connectivity applications.
What is SOI?
SOI or Silicon-on-Insulator refers to a technology where MOS device is fabricated on silicon-insulator-silicon substrate rather than conventional silicon. SOI MOSFET is fabricated as three layered device,the bottom most layer is the substrate which is lightly doped. The uniform buried layer of silicon dioxide which is called as buried oxide layer (BOX), supporting substrate or handle wafer or base wafer. The SOI is also a 4 terminal device source, drain, gate and the body. In SOI based devices Silicon junction and channel area are above electrical insulator like SiO2. Choice of insulator depends on application. Sapphire is used for high performance radio frequency (RF) and radiation sensitive application. SiO2 is used for microelectronics applications to minimise short channel effect. The width of the silicon film decides whether the SOI is fully depleted or partially depleted. If the width of SOI film laid over the buried oxide is thin, the device is said to be fully depleted or FDSOI. If the width of the SOI film is thick, it is said to be partially depleted or PDSOI. The thickness of the SOI layer for an FD-SOI MOSFET is usually about one-third the effective channel length in order to avoid a punch-through current. Thickness of BOX varies depending on application.
SOI Fabrication Process :
There are few unique ways to fabricate SOI Wafers, such as : SOS (Silicon On Sapphire ), Bonded and Etch back SOI, SIMOX (Separation By Implanted Oxygen), ELTRAN (Epitaxial Layer TRANsfer) , Smart-Cut .
i. Silicon on Sapphire (SOS) :
SOS wafers are formed by depositing Si onto the sapphire substrate at very high temperatures. Very pure sapphire crystal is grown in a controlled lab environment and the Si can be cleanly deposited on the surface of the sapphire wafer.
ii. Bonded and Etch back SOI (BESOI) :
Thermally oxidize the wafer. Another wafer is bonded over the previous one by method os SFB or Silicon Fusion Bonding. Silicon fusion bonding (SFB) is the joining together of two silicon wafers without the use of intermediate adhesives. Now the bonded wafer is etched to get the required thickness of SOI.
iii. SIMOX Method :
iv. SmartCut Fabrication Process :
v. ELTRAN (Epitaxial Layer TRANsfer):
Why VLSI Adopted SOI?
i. DIBL :
For a long-channel device a drain bias can change the effective channel length although the source barrier remain same. For a short channel device , the drain is closer to the source as compared to long channel device. So, drain bias can influence the barrier height at the source end. Figure shows the energy bands along the semiconductor surface. For a short-channel device, this lowered barrier with decreasing channel length or increasing drain bias is commonly called drain-induced barrier lowering (DIBL).
ii. Punch Through :
It a break down mechanism. Occurs when the sum of depletion layer width for source and drain junctions is comparable to the channel length. The depletion region of the drain and source junctions gradually merge together as the drain voltage is increased, causing current to flow irrespective of Vg at high Vd.
iii. CMOS-Latch Up :
Parasitic BJTs in a CMOS structure forms feedback loop and create a PNPN structure. Such latched up condition create low impedance path between Vdd and Vss. High current flows and the IC gets damaged.
iv. Junction Capacitance :
Cj = Junction Cap. Cd= Depletion Cap.
Cg = Gate Cap. Cov =Overlap Cap.
v. Leakage Current :
Gate Current Tunneling , Hot Carrier Injection
Subthrehold Current, Reverse Bias Jn. Current,
Gate Induced Drain Leakage, Channel Punch Through Current
Advantages of SOI :
SOI MOSFETs have a bunch of advantages compared to to trheir Bulk Silicon counterpart. Such as :
1. Reduction in : 1. Drain /source parasitic capacitances, 2. Delay,dynamic power consumption, 3. Leakage current.
2. Due to an oxide layer, the threshold voltage is less dependent on back gate bias compared to bulk CMOS. This makes the SOI device more suitable for low power applications.
3. SOI devices have no latch-up problems as there is no substrate to form PNPN structure.
5. SOI devices have excellent radiation hardness to alpha particles, neutrons, and other particles. Alpha particles are generated by small amounts of radioactive elements in IC materials.
6. SOI allows more devices per die area due to absence of wells and the possibility of direct contact of the source-drain diodes in the NMOS and PMOS transistors.
7. BOX coupled with ground plane (GP) suppress fringing electric fields through the BOX and substrate. So front-gate-to-channel control increases and DIBL lowers.
8. Faster device operation (speed/power product) due to reduction of parasitic capacitance (primarily due to reduced source-drain junction capacitance, but also from gate-to-substrate capacitance and metal-to- substrate capacitance).
9. Performance improvement happens equivalent to next technology node without scaling (e.g., performance of 0.25 micron devices on SOI wafers equivalent to performance of 0.18 micron devices on bulk wafers) .
10. Potential to simplify device fabrication steps. Fewer masks and ion implantation steps, made possible by the elimination of well and field isolation implants. Less complex (costly) lithography and etching required to achieve next-generation performance.
Performance of SOI MOSFET :
i. Threshold Voltage :
A thick-film SOI device, behaves like a bulk device due to absence of interaction between the front and back depletion regions, the threshold voltage is same as in a bulk device. For a thin- film SOI device, the threshold voltage is a function of the different possible steady-state charge conditions at the back interface.
ii. Body Effect :
In an SOI transistor, the body effect is defined as the dependence of the threshold voltage on the back-gate bias. In a thick film device, the body effecty (i.e. back-gate effect) is negligible due to absence of coupling between the front and back gate.
iii. Floating Body Effect : Floating body effect (FBE) is the major parasitic effect in SOI-MOSFETs and is a consequence of the complete isolation of the transistor from the substrate. The effect is related to the built-up of a positive charge in the Si body of the transistor, originating from the holes created by impact ionization. This charge cannot be removed rapidly enough, primarily because no contact with the Si film (body) is available. Self heating, bipolar currents and kink effect are said to be the major disadvantages of SOI technology when the body is left floating.
iv. Floating Body and Parasitic Bipolar Effects:
The presence of a floating volume of silicon under the gate is the origin of several effects, generically referred to as floating body effects. There exists a parasitic bipolar transistor in the MOS structure. If we consider an n-channel device, the N+ source, the P-type body and the N+ drain indeed form the emitter, the base, and the collector of an NPN bipolar transistor, respectively. In a bulk device, the base of the bipolar transistor is usually grounded by means of a substrate contact. But, due to the floating body in an SOI transistor, the base of the bipolar transistors is electrically floating. This parasitic bipolar transistor is origin of several undesirable effects in SOI devices.
v. Self Heating Effects:
Due to thermal isolation of substrate by the buried insulator in an SOI transistor, removal of excess heat generated by the Joule effect become critical. It leads to substantial elevation of device temperature. The excess heat mainly diffuses vertically through the buried oxide and laterally through the silicon island into the contacts and metallization. Due to the relatively low thermal conductivity of the buried oxide, the device heats up to 50 to 150C. This increase in device temperature leads to a reduction in mobility and current drive, thus degrading the device performance over a period of time.
vi. Kink Effect :
The kink effect is appearance of a kink in the output characteristics of an SOI MOSFET under strong inversion. The kink is very strong in n channel transistors, although absent from p-channel devices. In a thick-film or n-channel PD SOIMOSFET. When Vd is high enough, the channel electrons can acquire sufficient energy in the high electric field zone near the drain to create e-h pairs, due to an impact ionization mechanism. The generated electrons move into the channel and the drain, whereas the holes, which are majority carriers in the p-type body, migrate towards the place of lowest potential i.e., the floating body. The injection of holes into the floating body forward biases the source-body diode.The increase of body potential gives rise to lowering of threshold voltage and source-body potential barrier. More minority carriers are able to flow from source to the channel, thereby causing an excess drain current and producing many more pairs through the avalanche process. This positive feedback results in a sudden increase in Id or kink in output characteristics.
More on Kink Effect
FDSOI MOSFET and Kink Effect :
The electric field near the drain is lower in the FDSOI than in PDSOI. As a result, less electron-hole pair generation takes place in the fully depleted device. Also, in FDSOI, the source-to-body diode is already forward biased due to the full depletion of the film, and therefore, holes can readily combine in the source without having to raise the body potential there. That is why FDSOI is free of kink effect.
P-Channel SOI-MOSFET and Kink Effect :
The p-channel devices are free of kink effect because coefficient of electron-hole pair generation by energetic holes is much lower than that by energetic electrons. The kink effect is not observed in bulk devices as the majority carriers generated by impact ionization can escape into the substrate or to a well contact. The kink effect can be eliminated from the partially depleted SOI MOSFETs if a body contact is provided for removal of excess majority carriers from the device body.
Reducing Floating Body Effect
Body Contact :
Contacting silicon underneath the gate region to the ground effectively suppresses the kink effect as well as the parasitic lateral bipolar effects. Several schemes exist to provide the transistor with body contact. It consists of a P+ region which is in contact with the P-type silicon underneath the gate.
Source Body Tie Structure:
A more compact method, source body tie structure. P+ body ties are created on the side of the N+ source diffusion. If the device width is large, additional P+ regions can be formed in the source (such that a P+ N+ P+ N+ structure is introduced). Such a device has the main drawbacks of being asymmetrical (source and drain cannot be switched), and the effective channel width is smaller than the width of the active area.
FDSOI vs. PD SOI:
FDSOI devices are naturally free from kink effect .FD SOI has an enhanced sub-threshold swing, S . Therefore FD devices operate faster because of a sharper sub- threshold slope, and a reduced threshold voltage that allows for faster switching of the MOS transistors. These transistors also have increased drive currents at relatively low voltages. Fully-depleted SOI devices have the highest gains in circuit speed, reduced power requirements and highest level of soft-error immunity. Interface coupling effect affects operations of FDSOI. their operation. The interface coupling is inherent to fully depleted SOI devices, where all parameters (threshold voltage, trans-conductance, interface-trap response etc.) of one channel are insidiously affected by the opposite gate voltage (at the buried oxide). The threshold voltage fluctuation due to SOI thickness variation is one of the most serious problems in FD SOI MOSFETs. PDSOI devices are built on a thicker silicon layer and are simpler to manufacture. Most design features for developing PD devices can be imported from the bulk silicon devices and used in the SOI environment with only modest changes. This makes circuit redesign for the PD devices simpler than for the FD microcircuits.
In this comprehensive article , we delve into several crucial aspects of VLSI (Very Large Scale Integration) technology, providing an in-depth exploration of High-K Dielectrics. These discussions cover significant milestones in VLSI device development, and we shed light on the advantages of Silicon Dioxide (SiO2), which has been a cornerstone in semiconductor manufacturing. We demystify the concepts of Low-K and High-K Dielectrics, explaining why the latter is gaining prominence in modern semiconductor fabrication processes. We also address the pressing question of "Why High-K Dielectric?" by examining its pivotal role in enhancing the performance and efficiency of electronic components. Furthermore, we dive into the intricate domains of dielectric conductance and breakdown, elucidating the critical mechanisms and challenges in this field. The segments titled "Essential Qualities of High-K Dielectrics" provide a thorough breakdown of the key attributes and characteristics that make High-K Dielectrics indispensable in VLSI technology.
Finally, we explore the synergy between High-K Dielectrics and Metal Gate technologies, highlighting their interplay in advancing the capabilities of modern semiconductor devices. This article promises to be an enlightening resource for anyone interested in understanding the significance of High-K Dielectrics in the context of VLSI technology.
Major Device Milestone in VLSI :
Moore’s law has been driving and guiding force for last few decades for enhancement of device performance. To keep up with the pace of scaling, new ways found and introduced, such as :
1. new structure like FinFET, SOI, Nano Sheet FET
2. new material like Strained-Si, High-k dielectric
3. new interconnect material like Cu
Advantages of SiO2 :
Silicon dioxide is the main reason that microelectronics uses Si technology and not another semiconductor. As a semiconductor, Si has average performance, but in most respects SiO2 is an excellent insulator. SiO2 can be made from Si simply by thermal oxidation, whereas every other semiconductor (Ge, GaAs, GaN, SiC…) has a poor native oxide or poor interface with its oxide. SiO2 is amorphous, has very few electronic defects and forms an excellent, abrupt interface with Si. SiO2 can be etched and patterned to a nanometer scale. Its only problem is that it is possible to tunnel across it when very thin.
What are Low-K & High-K Dielectrics?
The dielectric constant, k, is a parameter defining ability of material to store charge. The k value of SiO2 is 3.9 and in si technology it is considered as reference. Dielectrics with k>3.9 are referred as “high”-k and dielectrics with k<3.9 are defined as “low”-k dielectrics. In state-of-art VLSi technology both high- and low-k dielectrics are needed and used for different reasons.
Need for high-k dielectric:
- SiO2 has been used as a gate oxide material for decades.
- The thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance, drive current and raising device performance. As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability.
- Use of high-k dielectric instead of SiO2 leads to increased gate capacitance while keeping gate oxide thickness fair enough so that leakage effects are reduced.
Need for low-k dielectric:
-In digital circuits, insulating dielectrics separate the conducting parts (wire interconnects and transistors) from one another. As components have scaled and transistors have gotten closer together, the insulating dielectrics have thinned to the point where charge build-up and crosstalk adversely affect the performance of the device. To reduce parasitic capacitance low-k dielectric is used instead of SiO2.
Why High-k Dielectric ?
Over last few decades scaling of MOSFET dimension has been been viewed as an effective approach to enhance transistor performance as predicted by Moore’s law. Scaling includes Gate Oxide thickness reduction. Reduction in the thickness of silicon dioxide gate dielectrics has enabled increased numbers of transistors per chip with enhanced circuit functionality and performance at low costs. As we approached sub-45 nm node, the effective oxide thickness (EOT) of the traditional silicon dioxide dielectrics are required to be smaller than 1 nm, which is approximately 3 monolayers and close to the physical limit. Such thin layer of Silicon is prone to high gate leakage current due to the obvious quantum tunneling effect at this scale. To continue the downward scaling, dielectrics with a higher dielectric constant (high-k) are being suggested as a solution to achieve the same transistor performance while maintaining a relatively thick physical thickness.
Dielectric Conductance & Breakdown :
Performance of MOS devices depends on the breakdown properties and the current transport behaviors of the gate dielectric. Ideally in an MOS structure, the conductance of the dielectric is assumed as zero. However in real world situation under high electric field/ temperature there is some carrier conduction. Tunneling is the conduction mechanism in insulators. Tunneling is a quantum mechanical phenomenon in which electron wave function can penetrate a potential barrier.
There are 4 different mechanism :
1. direct tunneling,
2. F-N tunneling,
3. Schottky Emission ,
4. Poole Frankel Emission
Under large bias, tunneling current flows through dielectric. When energetic carriers move through the insulator, defects are generated randomly in the bulk of the dielectric film. If number of defects are high enough to form a continuous path connecting the gate to the semiconductor, a conduction path is created and dielectric breakdown occurs.
Essential Qualities of High-k Dielectrics:
1. K value, band gap and band offset : To get high capacitance k value must be over 12, preferably 25–30. High-k value means, the dielectrics will have a reasonable physical thickness to prevent gate leakage. The layer must not be too thick to hamper physical scaling when achieving the target EOT. On the other hand, a very large k value is undesirable in CMOS design because they cause unfavorable large fringing fields at the source and drain regions. If a high-k dielectric can replace SiO2, the dielectric thickness (Tk) increases proportionally to keep the same dielectric capacitance. A figure of merit to judge a high-k gate dielectric layer is the equivalent oxide thickness, defined as EOT = (ε1/ε2)T where ε1= 3.9 , ε2 = k value of High-k material, T= High-k dielectric thickness.
2.Thermal stability : In present CMOS processes, the gate stacks must undergo rapid thermal annealing . This requires that the gate oxides must be thermally and chemically stable especially with the contacting materials. Additionally, oxides should not react with water. Among many high k dielectrics, HfO2 has both a high k value as well as chemical stability with water and Si.
3. Crystallization temperature : Amorphous materials are preferred to crystalline ones, owing to the absence of grains and good diffusion barrier properties. The grains present in the crystalline systems can often be the pathways for dopants diffusion and breakdown. Unlike SiO2, high-k oxides usually have low crystalline temperature and can easily crystallize when subjected to RTA. In particular, HfO2 and ZrO2 crystallize at much lower temperatures at ~400 oC and ~300 oC, respectively. According to the above factors, the approach to improve the crystallization temperature of HfO2 and ZrO2 should be considered. The crystallized HfO2 has a much lower leakage current.
4. Interface Quality :The interface between the high-k dielectrics and Si substrate must have the highest electrical quality and flatness, absence of interface defects, and low interface state density Dit. Bad interface quality can cause high fixed charge density, inducing a large shift in the flat band voltage (Vfb) which severely reduces the performance and reliability of the transistor.
5. O2 and dopant diffusion through the grain boundary
6. Compatibility with the gate electrode
7. Density of interface states comparable to SiO2
8. Low lattice mismatch and similar thermal expansion coefficient with Si
9. Mobility comparable to SiO2
High -k/Metal Gate:
To continue the downscaling, dielectrics with a higher dielectric constant (high-k) are being suggested. Many candidates of possible high-k gate dielectrics have been suggested to replace SiO2 and they include nitrided SiO2, Hf-based oxides, and Zr-based oxides. Hf-based oxides have been recently highlighted as the most suitable dielectric materials because of their comprehensive performance. One of the key issues regarding new gate dielectrics is the low crystallization temperature. Due ti this reason, it is difficult to integrate them into traditional CMOS processes. To solve these problems, additional elements such as N, Si, Al, Ti, Ta and La have been incorporated into the high-k gate dielectrics, especially Hf-based oxides. For the gate electrode, both poly-Si and different metals have been investigated along with high-κ dielectrics. The combination of a high-κ dielectric and a poly-Si gate is not suitable for high- performance logic applications since the resulting high-κ/poly-Si transistors have high threshold voltages and degraded channel mobility, and hence poor drive current performance. It has been proposed that the high threshold voltage is caused by Fermi level pinning at the poly-Si/high-κ dielectric interface and that Fermi level pinning is most likely caused by defect formation at that interface. It has been demonstrated both experimentally and theoretically that surface phonon scattering in high-κ dielectrics is the primary cause of channel mobility degradation. Significantly, metal gate electrodes are effective for screening phonon scattering in the high-κ dielectric from coupling to the channel when under inversion conditions. This results in improved channel mobility.
This article provides an extensive exploration of key aspects in VLSI technology. The discussion begins by examining milestones in the field and the significance of gate materials. It then delves into a detailed analysis of Poly Silicon, covering its nature and applications. Two segments are dedicated to understanding why Poly Silicon is utilized as a gate material. The video also elucidates the importance of the Self Aligned Process in semiconductor fabrication. A thorough examination of the Poly Depletion Effect follows, offering insights into its implications in VLSI design. The conclusion encompasses a comprehensive discussion on High-K Material and Poly-Si gate, shedding light on their roles in advancing VLSI technology.
VLSI Milestone & Gate Material :
Over last Few decades CMOS process has seen a strange transition from metal gate to Polysilicon gate to again metal gate. In earlier days Aluminium was used as gate material. Due to advantages of self aligned process industry moved to incorporation of Poly Silicon as gate material. With progressing node, again metal gate isintroduced in process. In this article we will discuss about the reasons behind these transitions.
What is Poly Silicon?
Polysilicon, poly-Si, multicrystalline Silicon,or polycrystalline silicon, is a material consisting of a number of smaller crystals or crystallites. It is made up of multiple small silicon crystals and is used in the solar and electronics industries.
Polycrystalline silicon is very popular in the solar industry since it is used in the production of solar cells, a key component in manufacturing solar panels. It has also found uses in various electronic devices, ranging from small components to automotive controls. There are three main methods to produce high-quality Poly-Silicon for use in different applications : The modified Siemens process, The fluidized bed reactor (FBR), process, The upgraded metallurgical-grade (UMG) silicon process.
Why Poly -Si Used as Gate?
In the early days Aluminum, was preferred for gate material of MOSFET. Later on, Poly -Si has gained preference.
Reasons behind it are:
1. CMOS fabrication involves high temperature process steps. Poly- Si melts at 1414 ˚C whereas Aluminum Melts at 660 ˚C. Diffusions and Anneals of Silicon Typically Require Around 1000 ˚ C causing any Aluminum present during processing to melt.
2. Poly Si supports self-aligned gates development. In case of Al gate Source and Drain must be formed prior to forming the gate. Causes misalignment of the Gate to the Source and Drain. To assure the overlapping of gate to the source and drain size of the gate is increased. Such misalignment of Gate cause substantial variability. This gate must be made approximately 3 times larger than the space between the source and drain to insure that this whole region is spanned. This results in a slow device the characteristics of which are strongly affected by the random misalignment of this gate element.
3. Undoped polysilicon has high resistivity. It is doped in such a way that its resistance is reduced. Heavy doping of Poly-si generates highly conductive gates required to form the device
4. Polysilicon is a Semiconductor its work function can be modulated by adjusting level of doping. Threshold voltage of MOSFET is related with work function difference between gate and channel material. The work function of a semiconductor qϕs is the energy difference between the vacuum level and the Fermi level and that varies with thedoping concentration. For a given metal with a fixed work function qϕm , work function difference qϕms ≡ (q ϕm – q ϕs) will vary depending on the doping of the semiconductor. Work function of Poly-Si can be varied with level of doping.
5. With proceeding nodes device dimensions reduced and their operating voltages also scaled down. For such situatiion low Vt MOSFETs required. Poly-Si gate MOSFET has lower Vt. Since Highly doped Poly -Si is used as gate material, its work function can be modulated by adjusting the level of doping.
6. Fabrication steps with Poly Silicon are less. Fabrication process specially mask creation and aligning is a critical and expensive process.
Why Self Aligned process is so preferred?
Performance Benefits :
1. Reduce the overlap capacitance.
2. Reduce the variability of overlap capacitance.
3. Reduce the threshold voltage of the PMOS transistors being used in MOSFETs at that time by 1.1 V
4. Workfunction difference between P-Doped Poly-Si gate and the substrate 1.1V lower than for Al
5. Lowered threshold voltage by 1.1 V or 30%
6. Increased speed by 3 to 5 times at same power dissipation
7. Reduced power by 3 to 5 times at same speed
8. Substantially reduced variability in device performance
9. Reduced silicon area and cost by approximately one half
10. Gate area substantially reduced by smaller gate
11. Polysilicon used as local interconnect increasing
routability and reducing area
12. Enabled use of Phosphosilicate Glass/PSG, which
requires higher temperature processing
Poly Depletion Effect :
Undoped Poly-Si has high resistivity. Highly doped Poly-Si is a good conductor. A heavily doped film of Poly-Si is used as the gate electrode material. Electrically active dopant concentrartion is usually less than 1X10^23 cm-3 . Poly-Si gates must be considered as semiconductor rather than a metal. Polysilicon Depletion effect is the phenomenon in which unwanted variation in Vth is observed when polysilicon is used as gate material. That leads to unpredictable behavior of the electronic circuit.
When voltage applied at gate terminal (+ve voltage in n channel MOSFET and -ve voltage in p-channel MOSFET)free carriers in highly doped polysilicon move towards the gate electrode and zone near the oxide get depleted of free carriers. This is basically depletion of polysilicon. This depleted zone contributes in effective gate oxide thickness and capacitance of this zone is added with gate oxide capacitance. This effect is known as polydepletion effect. Polydepletion leads effective increase of the dielectric thickness and an increase of the threshold voltage. Because of this High-k Dielectric/metal gates were introduced to solve the issue.
High-K Material & Poly-Si Gate:
At smaller nodes, leakege in MOSFET is predominant. Higher conductivity in the gate has also become important as the oxide dielectric layers cannot be shrunk any further to increase speed. As a result dielectric material with high k value is used as gate oxide. Poly Si and High-K material interact at high temperatures - creating Salicides. This thin (1–4 nm) layer have undesirable and unnecessary electrical impact on device performace. The compatibility and integration of high k dielectrics with polysilicon in existing CMOS process,within appropriate thermal budgets is one of the critical issues to implement high k materials into sub 0.1 um VLSI device fabrications. Various interfacial reactions take place during poly deposition at higher temperature (> 500 C). Interfacial reactions can be further enhanced during subsequent source/drain anneal where temperarture rise upto ~1000 oC in CMOS processing. Another issue with PolySi/High-K combination is that threshold voltage become unacceptably (specially at advanced node) high. As a result , metal gates are used with a high-k dielectric CMOS processing.
